src/soc/fu/mmu/fsm.py

   1 """
   2 Based on microwatt mmu.vhdl
   3
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=491
   5 * https://bugs.libre-soc.org/show_bug.cgi?id=450
   6 """
   7
   8 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   9 from nmigen import Record, Memory
  10 from nmigen import Const
  11 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
  12 from nmutil.singlepipe import ControlBase
  13 from nmutil.util import rising_edge
  14
  15 from soc.experiment.mmu import MMU
  16
  17 from openpower.consts import MSR
  18 from openpower.decoder.power_fields import DecodeFields
  19 from openpower.decoder.power_fieldsn import SignalBitRange
  20 from openpower.decoder.power_decoder2 import decode_spr_num
  21 from openpower.decoder.power_enums import MicrOp
  22
  23 from soc.experiment.mem_types import LoadStore1ToMMUType
  24 from soc.experiment.mem_types import MMUToLoadStore1Type
  25
  26 from soc.fu.ldst.loadstore import LoadStore1, TestSRAMLoadStore1
  27 from nmutil.util import Display
  28
  29 class FSMMMUStage(ControlBase):
  30     """FSM MMU
  31
  32     FSM-based MMU: must call set_ldst_interface and pass in an instance
  33     of a LoadStore1.  this to comply with the ConfigMemoryPortInterface API
  34
  35     this Function Unit is extremely unusual in that it actually stores a
  36     "thing" rather than "processes inputs and produces outputs".  hence
  37     why it has to be a FSM.  linking up LD/ST however is going to have
  38     to be done back in Issuer (or Core).  sorted: call set_ldst_interface
  39     """
  40     def __init__(self, pspec):
  41         super().__init__()
  42         self.pspec = pspec
  43
  44         # set up p/n data
  45         self.p.i_data = MMUInputData(pspec)
  46         self.n.o_data = MMUOutputData(pspec)
  47
  48         self.mmu = MMU()
  49
  50         # debugging output for gtkw
  51         self.debug0 = Signal(4)
  52         self.illegal = Signal()
  53
  54         # for SPR field number access
  55         i = self.p.i_data
  56         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
  57         self.fields.create_specs()
  58
  59     def set_ldst_interface(self, ldst):
  60         """must be called back in Core, after FUs have been set up.
  61         one of those will be the MMU (us!) but the LoadStore1 instance
  62         must be set up in ConfigMemoryPortInterface. sigh.
  63         """
  64         # incoming PortInterface
  65         self.ldst = ldst
  66         self.dcache = self.ldst.dcache
  67         self.pi = self.ldst.pi
  68
  69     def elaborate(self, platform):
  70         assert hasattr(self, "dcache"), "remember to call set_ldst_interface"
  71         m = super().elaborate(platform)
  72         comb, sync = m.d.comb, m.d.sync
  73         dcache = self.dcache
  74
  75         # link mmu and dcache together
  76         m.submodules.mmu = mmu = self.mmu
  77         ldst = self.ldst # managed externally: do not add here
  78         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
  79         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
  80
  81         l_in, l_out = mmu.l_in, mmu.l_out
  82         d_in, d_out = dcache.d_in, dcache.d_out
  83         wb_out, wb_in = dcache.wb_out, dcache.wb_in
  84
  85         # link ldst and MMU together
  86         comb += l_in.eq(ldst.m_out)
  87         comb += ldst.m_in.eq(l_out)
  88
  89         i_data, o_data = self.p.i_data, self.n.o_data
  90         a_i, b_i, o, spr1_o = i_data.ra, i_data.rb, o_data.o, o_data.spr1
  91         op = i_data.ctx.op
  92         msr_i = op.msr
  93         spr1_i = i_data.spr1
  94
  95         # these are set / got here *ON BEHALF* of LoadStore1
  96         dsisr, dar = ldst.dsisr, ldst.dar
  97
  98         # busy/done signals
  99         busy = Signal()
 100         done = Signal()
 101         m.d.comb += self.n.o_valid.eq(busy & done)
 102         m.d.comb += self.p.o_ready.eq(~busy)
 103
 104         # take copy of X-Form SPR field
 105         x_fields = self.fields.FormXFX
 106         spr = Signal(len(x_fields.SPR))
 107         comb += spr.eq(decode_spr_num(x_fields.SPR))
 108
 109         # based on MSR bits, set priv and virt mode.  TODO: 32-bit mode
 110         comb += d_in.priv_mode.eq(~msr_i[MSR.PR])
 111         comb += d_in.virt_mode.eq(msr_i[MSR.DR])
 112         #comb += d_in.mode_32bit.eq(msr_i[MSR.SF]) # ?? err
 113
 114         # ok so we have to "pulse" the MMU (or dcache) rather than
 115         # hold the valid hi permanently.  guess what this does...
 116         valid = Signal()
 117         blip = Signal()
 118         m.d.comb += blip.eq(rising_edge(m, valid))
 119
 120         with m.If(~busy):
 121             with m.If(self.p.i_valid):
 122                 sync += busy.eq(1)
 123         with m.Else():
 124
 125             # based on the Micro-Op, we work out which of MMU or DCache
 126             # should "action" the operation.  one of MMU or DCache gets
 127             # enabled ("valid") and we twiddle our thumbs until it
 128             # responds ("done").
 129
 130             # WIP: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 131
 132             with m.Switch(op.insn_type):
 133                 with m.Case(MicrOp.OP_MTSPR):
 134                     # despite redirection this FU **MUST** behave exactly
 135                     # like the SPR FU.  this **INCLUDES** updating the SPR
 136                     # regfile because the CSV file entry for OP_MTSPR
 137                     # categorically defines and requires the expectation
 138                     # that the CompUnit **WILL** write to the regfile.
 139                     comb += spr1_o.data.eq(a_i)
 140                     comb += spr1_o.ok.eq(1)
 141                     # subset SPR: first check a few bits
 142                     # XXX NOTE this must now cover **FOUR** values: this
 143                     # test might not be adequate.  DSISR, DAR, PGTBL and PID
 144                     # must ALL be covered here.
 145                     with m.If(~spr[9] & ~spr[5]):
 146                         comb += self.debug0.eq(3)
 147                         #if matched update local cached value
 148                         #commented out because there is a driver conflict
 149                         #with m.If(spr[0]):
 150                         #    sync += dsisr.eq(a_i[:32])
 151                         #with m.Else():
 152                         #    sync += dar.eq(a_i)
 153                         comb += done.eq(1)
 154                     # pass it over to the MMU instead
 155                     with m.Else():
 156                         # PGTBL and PID
 157                         comb += self.debug0.eq(4)
 158                         # blip the MMU and wait for it to complete
 159                         comb += valid.eq(1)   # start "pulse"
 160                         comb += l_in.valid.eq(blip)   # start
 161                         comb += l_in.mtspr.eq(1)      # mtspr mode
 162                         comb += l_in.sprn.eq(spr)  # which SPR
 163                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 164                         comb += done.eq(1) # FIXME l_out.done
 165
 166                 with m.Case(MicrOp.OP_MFSPR):
 167                     comb += o.data.eq(spr1_i)
 168                     comb += o.ok.eq(1)
 169                     comb += done.eq(1)
 170
 171                 with m.Case(MicrOp.OP_TLBIE):
 172                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 173                     # note that the spr is *not* an actual spr number, it's
 174                     # just that those bits happen to match with field bits
 175                     # RIC, PRS, R
 176                     comb += Display("TLBIE: %i %i",spr,l_out.done)
 177                     comb += valid.eq(1)   # start "pulse"
 178                     comb += l_in.valid.eq(blip)   # start
 179                     comb += l_in.tlbie.eq(1)   # mtspr mode
 180                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 181                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 182                     comb += done.eq(l_out.done) # zzzz
 183                     comb += self.debug0.eq(2)
 184
 185                 with m.Case(MicrOp.OP_ILLEGAL):
 186                     comb += self.illegal.eq(1)
 187
 188             with m.If(self.n.i_ready & self.n.o_valid):
 189                 sync += busy.eq(0)
 190
 191         return m
 192
 193     def __iter__(self):
 194         yield from self.p
 195         yield from self.n
 196
 197     def ports(self):
 198         return list(self)