src/soc/fu/mmu/test/test_issuer_mmu_rom.py

   1 from nmigen import Module, Signal
   2 from soc.simple.test.test_runner_mmu_rom import TestRunner
   3 from soc.simulator.program import Program
   4 from soc.config.endian import bigendian
   5 import unittest
   6
   7 from soc.fu.test.common import (
   8     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
   9
  10 def b(x):
  11     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  12                           byteorder='big', signed=False)
  13 default_mem = { 0x10000:    # PARTITION_TABLE_2
  14                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  15                 b(0x800000000100000b),
  16
  17                 0x30000:     # RADIX_ROOT_PTE
  18                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  19                 b(0x8000000000040009),
  20
  21                 0x40000:     # RADIX_SECOND_LEVEL
  22                         #          V = 1 L = 1 SW = 0 RPN = 0
  23                            # R = 1 C = 1 ATT = 0 EAA 0x7
  24                 b(0xc000000000000187),
  25
  26                 0x1000000:   # PROCESS_TABLE_3
  27                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  28                 b(0x40000000000300ad),
  29             }
  30
  31
  32 class MMUTestCase(TestAccumulatorBase):
  33     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  34     # libre-soc has own SPR unit
  35     # other instructions here -> must be load/store
  36
  37     def case_mmu_ldst(self):
  38         lst = [
  39                 "mtspr 720, 1",
  40                 "lhz 3, 0(1)"      # load some data
  41               ]
  42
  43         initial_regs = [0] * 32
  44
  45         prtbl = 0x1000000
  46         initial_regs[1] = prtbl
  47
  48
  49         initial_sprs = {}
  50         self.add_case(Program(lst, bigendian),
  51                       initial_regs, initial_sprs)
  52 class RomDBG():
  53     def __init__(self):
  54         self.rom = default_mem
  55         self.debug = open("/tmp/rom.log","w")
  56
  57         # yield mmu.rin.prtbl.eq(0x1000000) # set process table -- SPR_PRTBL = 720
  58
  59 rom_dbg = RomDBG()
  60
  61 if __name__ == "__main__":
  62     unittest.main(exit=False)
  63     suite = unittest.TestSuite()
  64     suite.addTest(TestRunner(MMUTestCase().test_data,rom_dbg))
  65     runner = unittest.TextTestRunner()
  66     runner.run(suite)