src/soc/fu/mmu/test/test_non_production_core.py

   1 from nmigen import Module, Signal
   2
   3 from nmutil.sim_tmp_alternative import Simulator, Settle
   4
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from openpower.decoder.isa.caller import ISACaller, special_sprs
   8 from openpower.decoder.power_decoder import (create_pdecode)
   9 from openpower.decoder.power_decoder2 import (PowerDecode2)
  10 from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
  11 from openpower.decoder.selectable_int import SelectableInt
  12 from openpower.simulator.program import Program
  13 from openpower.decoder.isa.all import ISA
  14 from soc.config.endian import bigendian
  15 from openpower.consts import MSR
  16
  17
  18 from openpower.test.common import (
  19     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
  20 import random
  21
  22 from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
  23                                     set_alu_inputs, DivTestHelper)
  24
  25 from soc.simple.core import NonProductionCore
  26 from soc.config.test.test_loadstore import TestMemPspec
  27 from soc.simple.test.test_core import (setup_regs, check_regs,
  28                                        wait_for_busy_clear,
  29                                        wait_for_busy_hi)
  30
  31 debughang = 2
  32
  33 class MMUTestCase(TestAccumulatorBase):
  34     # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
  35     # other instructions here -> must be load/store
  36
  37     def case_mfspr_after_invalid_load(self):
  38         lst = [ # TODO -- set SPR on both sinulator and port interface
  39                 "mfspr 1, 18", # DSISR to reg 1
  40                 "mfspr 2, 19", # DAR to reg 2
  41                 # TODO -- verify returned sprvals
  42               ]
  43
  44         initial_regs = [0] * 32
  45
  46         #THOSE are currently broken -- initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
  47         initial_sprs = {}
  48         self.add_case(Program(lst, bigendian),
  49                       initial_regs, initial_sprs)
  50
  51     #def case_ilang(self):
  52     #    pspec = SPRPipeSpec(id_wid=2)
  53     #    alu = SPRBasePipe(pspec)
  54     #    vl = rtlil.convert(alu, ports=alu.ports())
  55     #    with open("trap_pipeline.il", "w") as f:
  56     #        f.write(vl)
  57
  58
  59 class TestRunner(unittest.TestCase):
  60     def __init__(self, test_data):
  61         super().__init__("run_all")
  62         self.test_data = test_data
  63
  64     def execute(self, core, instruction, pdecode2, test):
  65         program = test.program
  66         sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
  67                   test.mem, test.msr,
  68                   bigendian=bigendian)
  69         gen = program.generate_instructions()
  70         instructions = list(zip(gen, program.assembly.splitlines()))
  71
  72         pc = sim.pc.CIA.value
  73         msr = sim.msr.value
  74         index = pc//4
  75         while index < len(instructions):
  76             ins, code = instructions[index]
  77
  78             print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
  79             print(code)
  80
  81             if 'XER' in sim.spr:
  82                 so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  83                 ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
  84                 ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
  85                 print("before: so/ov/32", so, ov, ov32)
  86
  87             # ask the decoder to decode this binary data (endian'd)
  88             yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
  89             yield pdecode2.state.msr.eq(msr)  # set MSR in pdecode2
  90             yield pdecode2.state.pc.eq(pc)  # set PC in pdecode2
  91             yield instruction.eq(ins)          # raw binary instr.
  92             yield Settle()
  93
  94             yield from setup_regs(pdecode2, core, test)
  95
  96             opname = code.split(' ')[0]
  97             yield from sim.call(opname)
  98             pc = sim.pc.CIA.value
  99             msr = sim.msr.value
 100             index = pc//4
 101             print("pc after %08x" % (pc))
 102
 103             fsm = core.fus.fus["mmu0"].alu
 104
 105             vld = yield fsm.n.valid_o
 106             while not vld:
 107                 yield
 108                 if debughang:  print("not valid -- hang")
 109                 vld = yield fsm.n.valid_o
 110                 if debughang==2: vld=1
 111             yield
 112
 113     def run_all(self):
 114         m = Module()
 115         comb = m.d.comb
 116         instruction = Signal(32)
 117
 118         pdecode = create_pdecode()
 119
 120         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 121
 122         pspec = TestMemPspec(ldst_ifacetype='testpi',
 123                              imem_ifacetype='',
 124                              addr_wid=48,
 125                              mask_wid=8,
 126                              reg_wid=64)
 127
 128         m.submodules.core = core = NonProductionCore(pspec
 129                                      # XXX NO absolutely do not do this.
 130                                      # all options must go into the pspec
 131                                      #, microwatt_mmu=True
 132                                                         )
 133
 134         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 135         sim = Simulator(m)
 136
 137         sim.add_clock(1e-6)
 138
 139         def process():
 140             for test in self.test_data:
 141                 print("test", test.name)
 142                 print("sprs", test.sprs)
 143                 program = test.program
 144                 with self.subTest(test.name):
 145                     yield from self.execute(core, instruction, pdecode2, test)
 146
 147         sim.add_sync_process(process)
 148         with sim.write_vcd("mmu_ldst_simulator.vcd", "mmu_ldst_simulator.gtkw",
 149                            traces=[]):
 150             sim.run()
 151
 152 if __name__ == "__main__":
 153     unittest.main(exit=False)
 154     suite = unittest.TestSuite()
 155     suite.addTest(TestRunner(MMUTestCase().test_data))
 156
 157     runner = unittest.TextTestRunner()
 158     runner.run(suite)