src/soc/fu/mul/main_stage.py

   1 # This stage is intended to do the main work of an actual multiply
   2
   3 from nmigen import Module
   4 from nmutil.pipemodbase import PipeModBase
   5 from soc.fu.mul.pipe_data import MulIntermediateData, MulOutputData
   6 from ieee754.part.partsig import PartitionedSignal
   7
   8
   9 class MulMainStage2(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "mul2")
  12
  13     def ispec(self):
  14         return MulIntermediateData(self.pspec) # pipeline stage input format
  15
  16     def ospec(self):
  17         return MulOutputData(self.pspec) # pipeline stage output format
  18
  19     def elaborate(self, platform):
  20         m = Module()
  21         comb = m.d.comb
  22
  23         # convenience variables
  24         a, b, o = self.i.a, self.i.b, self.o.o
  25
  26         # actual multiply (TODO: split into stages)
  27         # it's ironic that one line of code can create 15,000 gates...
  28         comb += o.eq(a * b)
  29
  30         ###### xer and context, all pass-through #####
  31
  32         comb += self.o.neg_res.eq(self.i.neg_res)
  33         comb += self.o.neg_res32.eq(self.i.neg_res32)
  34         comb += self.o.xer_so.eq(self.i.xer_so)
  35         comb += self.o.ctx.eq(self.i.ctx)
  36
  37         return m
  38