src/soc/fu/mul/output_stage.py

   1 # This stage is intended to adjust the input data before sending it to
   2 # the actual ALU. Things like handling inverting the input, xer_ca
   3 # generation for subtraction, and handling of immediates should happen
   4 # in the base class (CommonOutputStage.elaborate).
   5 from soc.fu.alu.output_stage import ALUOutputStage
   6 from soc.fu.div.pipe_data import DivMulOutputData
   7
   8 # simply over-ride ALUOutputStage ispec / ospec
   9 class DivMulOutputStage(ALUOutputStage):
  10     def ispec(self): return DivMulOutputData(self.pspec)
  11     def ospec(self): return DivMulOutputData(self.pspec)
  12