src/soc/fu/regspec.py

   1 """RegSpecs
   2
   3 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
   4
   5 this module is a key strategic module that links pipeline specifications
   6 (soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits.  MultiCompUnits
   7 know absolutely nothing about the data passing through them: all they know
   8 is: how many inputs they need to manage, and how many outputs.
   9
  10 regspecs tell MultiCompUnit what the ordering of the inputs is, how many to
  11 create, and how to connect them up to the ALU being "managed" by this CompUnit.
  12 likewise for outputs.
  13
  14 later (TODO) the Register Files will be connected to MultiCompUnits, and,
  15 again, the regspecs will say which Regfile (which type) is connected to
  16 which MultiCompUnit port, how wide the connection is, and so on.
  17
  18 """
  19
  20
  21 def get_regspec_bitwidth(regspec, srcdest, idx):
  22     bitspec = regspec[srcdest][idx]
  23     wid = 0
  24     print (bitspec)
  25     for ranges in bitspec[2].split(","):
  26         ranges = ranges.split(":")
  27         print (ranges)
  28         if len(ranges) == 1: # only one bit
  29             wid += 1
  30         else:
  31             start, end = map(int, ranges)
  32             wid += (end-start)+1
  33     return wid
  34
  35
  36 class RegSpec:
  37     def __init__(self, rwid, n_src=None, n_dst=None, name=None):
  38         self._rwid = rwid
  39         if isinstance(rwid, int):
  40             # rwid: integer (covers all registers)
  41             self._n_src, self._n_dst = n_src, n_dst
  42         else:
  43             # rwid: a regspec.
  44             self._n_src, self._n_dst = len(rwid[0]), len(rwid[1])
  45
  46     def _get_dstwid(self, i):
  47         if isinstance(self._rwid, int):
  48             return self._rwid
  49         return get_regspec_bitwidth(self._rwid, 1, i)
  50
  51     def _get_srcwid(self, i):
  52         if isinstance(self._rwid, int):
  53             return self._rwid
  54         return get_regspec_bitwidth(self._rwid, 0, i)
  55
  56
  57 class RegSpecALUAPI:
  58     def __init__(self, rwid, alu):
  59         """RegSpecAPI
  60
  61         * :rwid:       regspec
  62         * :alu:        ALU covered by this regspec
  63         """
  64         self.rwid = rwid
  65         self.alu = alu # actual ALU - set as a "submodule" of the CU
  66
  67     def get_out(self, i):
  68         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  69             return self.alu.out[i]
  70         # regspec-based API: look up variable through regspec thru row number
  71         return getattr(self.alu.n.data_o, self.rwid[1][i][1])
  72
  73     def get_in(self, i):
  74         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  75             return self.alu.i[i]
  76         # regspec-based API: look up variable through regspec thru row number
  77         return getattr(self.alu.p.data_i, self.rwid[0][i][1])
  78
  79     def get_op(self):
  80         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
  81             return self.alu.op
  82         return self.alu.p.data_i.ctx.op