src/soc/fu/shift_rot/rotator.py

   1 # Manual translation and adaptation of rotator.vhdl from microwatt into nmigen
   2 #
   3 from nmigen.compat.sim import run_simulation
   4
   5 from nmigen import (Elaboratable, Signal, Module, Const, Cat, Repl,
   6                     unsigned, signed)
   7 from soc.fu.shift_rot.rotl import ROTL
   8 from nmutil.extend import exts
   9 from nmigen.back.pysim import Settle
  10
  11
  12 # note BE bit numbering
  13 def right_mask(m, mask_begin):
  14     ret = Signal(64, name="right_mask", reset_less=True)
  15     with m.If(mask_begin <= 64):
  16         m.d.comb += ret.eq((1 << (64-mask_begin)) - 1)
  17     return ret
  18
  19
  20 def left_mask(m, mask_end):
  21     ret = Signal(64, name="left_mask", reset_less=True)
  22     m.d.comb += ret.eq(~((1 << (63-mask_end)) - 1))
  23     return ret
  24
  25
  26 class Rotator(Elaboratable):
  27     """Rotator: covers multiple POWER9 rotate functions
  28
  29         supported modes:
  30
  31         * sl[wd]
  32         * rlw*, rldic, rldicr, rldimi
  33         * rldicl, sr[wd]
  34         * sra[wd][i]
  35
  36         use as follows:
  37
  38         * shift = RB[0:7]
  39         * arith = 1 when is_signed
  40         * right_shift = 1 when insn_type is OP_SHR
  41         * clear_left = 1 when insn_type is OP_RLC or OP_RLCL
  42         * clear_right = 1 when insn_type is OP_RLC or OP_RLCR
  43     """
  44
  45     def __init__(self):
  46         # input
  47         self.me = Signal(5, reset_less=True)        # ME field
  48         self.mb = Signal(5, reset_less=True)        # MB field
  49         # extra bit of mb in MD-form
  50         self.mb_extra = Signal(1, reset_less=True)
  51         self.ra = Signal(64, reset_less=True)       # RA
  52         self.rs = Signal(64, reset_less=True)       # RS
  53         self.shift = Signal(7, reset_less=True)     # RB[0:7]
  54         self.is_32bit = Signal(reset_less=True)
  55         self.right_shift = Signal(reset_less=True)
  56         self.arith = Signal(reset_less=True)
  57         self.clear_left = Signal(reset_less=True)
  58         self.clear_right = Signal(reset_less=True)
  59         self.sign_ext_rs = Signal(reset_less=True)
  60         # output
  61         self.result_o = Signal(64, reset_less=True)
  62         self.carry_out_o = Signal(reset_less=True)
  63
  64     def elaborate(self, platform):
  65         m = Module()
  66         comb = m.d.comb
  67         ra, rs = self.ra, self.rs
  68
  69         # temporaries
  70         rot_count = Signal(6, reset_less=True)
  71         rot = Signal(64, reset_less=True)
  72         sh = Signal(7, reset_less=True)
  73         mb = Signal(7, reset_less=True)
  74         me = Signal(7, reset_less=True)
  75         mr = Signal(64, reset_less=True)
  76         ml = Signal(64, reset_less=True)
  77         output_mode = Signal(2, reset_less=True)
  78         hi32 = Signal(32, reset_less=True)
  79         repl32 = Signal(64, reset_less=True)
  80
  81         # First replicate bottom 32 bits to both halves if 32-bit
  82         with m.If(self.is_32bit):
  83             comb += hi32.eq(rs[0:32])
  84         with m.Elif(self.sign_ext_rs):
  85             # sign-extend bottom 32 bits
  86             comb += hi32.eq(Repl(rs[31], 32))
  87         with m.Else():
  88             comb += hi32.eq(rs[32:64])
  89         comb += repl32.eq(Cat(rs[0:32], hi32))
  90
  91         shift_signed = Signal(signed(6))
  92         comb += shift_signed.eq(self.shift[0:6])
  93
  94         # Negate shift count for right shifts
  95         with m.If(self.right_shift):
  96             comb += rot_count.eq(-shift_signed)
  97         with m.Else():
  98             comb += rot_count.eq(self.shift[0:6])
  99
 100         # ROTL submodule
 101         m.submodules.rotl = rotl = ROTL(64)
 102         comb += rotl.a.eq(repl32)
 103         comb += rotl.b.eq(rot_count)
 104         comb += rot.eq(rotl.o)
 105
 106         # Trim shift count to 6 bits for 32-bit shifts
 107         comb += sh.eq(Cat(self.shift[0:6], self.shift[6] & ~self.is_32bit))
 108
 109         # XXX errr... we should already have these, in Fields?  oh well
 110         # Work out mask begin/end indexes (caution, big-endian bit numbering)
 111
 112         # mask-begin (mb)
 113         with m.If(self.clear_left):
 114             comb += mb.eq(self.mb)
 115             with m.If(self.is_32bit):
 116                 comb += mb[5:7].eq(Const(0b01, 2))
 117             with m.Else():
 118                 comb += mb[5:7].eq(Cat(self.mb_extra, Const(0b0, 1)))
 119         with m.Elif(self.right_shift):
 120             # this is basically mb = sh + (is_32bit? 32: 0);
 121             comb += mb.eq(sh)
 122             with m.If(self.is_32bit):
 123                 comb += mb[5:7].eq(Cat(~sh[5], sh[5]))
 124         with m.Else():
 125             comb += mb.eq(Cat(Const(0b0, 5), self.is_32bit, Const(0b0, 1)))
 126
 127         # mask-end (me)
 128         with m.If(self.clear_right & self.is_32bit):
 129             # TODO: track down where this is.  have to use fields.
 130             comb += me.eq(Cat(self.me, Const(0b01, 2)))
 131         with m.Elif(self.clear_right & ~self.clear_left):
 132             # this is me, have to use fields
 133             comb += me.eq(Cat(self.mb, self.mb_extra, Const(0b0, 1)))
 134         with m.Else():
 135             # effectively, 63 - sh
 136             comb += me.eq(Cat(~sh[0:6], sh[6]))
 137
 138         # Calculate left and right masks
 139         comb += mr.eq(right_mask(m, mb))
 140         comb += ml.eq(left_mask(m, me))
 141
 142         # Work out output mode
 143         # 00 for sl[wd]
 144         # 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
 145         # 10 for rldicl, sr[wd]
 146         # 1z for sra[wd][i], z = 1 if rs is negative
 147         with m.If((self.clear_left & ~self.clear_right) | self.right_shift):
 148             comb += output_mode.eq(Cat(self.arith & repl32[63], Const(1, 1)))
 149         with m.Else():
 150             mbgt = self.clear_right & (mb[0:6] > me[0:6])
 151             comb += output_mode.eq(Cat(mbgt, Const(0, 1)))
 152
 153         # Generate output from rotated input and masks
 154         with m.Switch(output_mode):
 155             with m.Case(0b00):
 156                 comb += self.result_o.eq((rot & (mr & ml)) | (ra & ~(mr & ml)))
 157             with m.Case(0b01):
 158                 comb += self.result_o.eq((rot & (mr | ml)) | (ra & ~(mr | ml)))
 159             with m.Case(0b10):
 160                 comb += self.result_o.eq(rot & mr)
 161             with m.Case(0b11):
 162                 comb += self.result_o.eq(rot | ~mr)
 163                 # Generate carry output for arithmetic shift right of -ve value
 164                 comb += self.carry_out_o.eq((rs & ~ml).bool())
 165
 166         return m
 167
 168
 169 if __name__ == '__main__':
 170
 171     m = Module()
 172     comb = m.d.comb
 173     mr = Signal(64)
 174     mb = Signal(6)
 175     comb += mr.eq(left_mask(m, mb))
 176
 177     def loop():
 178         for i in range(64):
 179             yield mb.eq(63-i)
 180             yield Settle()
 181             res = yield mr
 182             print(i, hex(res))
 183
 184     run_simulation(m, [loop()],
 185                    vcd_name="test_mask.vcd")