src/soc/fu/spr/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.spr.pipeline import SPRBasePipe
  17 from soc.fu.spr.pipe_data import SPRPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to SPRFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1
  29     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
  30     yield from ALUHelpers.get_sim_xer_ov(res, sim, dec2) # XER.ov
  31     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
  32
  33     print ("spr get_cu_inputs", res)
  34
  35     return res
  36
  37
  38
  39 def set_alu_inputs(alu, dec2, sim):
  40     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  41     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  42     # and place it into data_i.b
  43
  44     inp = yield from get_cu_inputs(dec2, sim)
  45     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  46     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  47     yield from ALUHelpers.set_xer_ov(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  49
  50     # XXX TODO slow spr1
  51     yield from ALUHelpers.set_fast_spr1(alu, dec2, inp)
  52
  53
  54 # This test bench is a bit different than is usual. Initially when I
  55 # was writing it, I had all of the tests call a function to create a
  56 # device under test and simulator, initialize the dut, run the
  57 # simulation for ~2 cycles, and assert that the dut output what it
  58 # should have. However, this was really slow, since it needed to
  59 # create and tear down the dut and simulator for every test case.
  60
  61 # Now, instead of doing that, every test case in SPRTestCase puts some
  62 # data into the test_data list below, describing the instructions to
  63 # be tested and the initial state. Once all the tests have been run,
  64 # test_data gets passed to TestRunner which then sets up the DUT and
  65 # simulator once, runs all the data through it, and asserts that the
  66 # results match the pseudocode sim at every cycle.
  67
  68 # By doing this, I've reduced the time it takes to run the test suite
  69 # massively. Before, it took around 1 minute on my computer, now it
  70 # takes around 3 seconds
  71
  72
  73 class SPRTestCase(FHDLTestCase):
  74     test_data = []
  75
  76     def __init__(self, name):
  77         super().__init__(name)
  78         self.test_name = name
  79
  80     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  81         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  82         self.test_data.append(tc)
  83
  84     def test_1_mfspr(self):
  85         lst = ["mfspr 1, 26", # SRR0
  86                "mfspr 2, 27",] # SRR1
  87         initial_regs = [0] * 32
  88         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
  89         self.run_tst_program(Program(lst), initial_regs, initial_sprs)
  90
  91     def test_ilang(self):
  92         pspec = SPRPipeSpec(id_wid=2)
  93         alu = SPRBasePipe(pspec)
  94         vl = rtlil.convert(alu, ports=alu.ports())
  95         with open("trap_pipeline.il", "w") as f:
  96             f.write(vl)
  97
  98
  99 class TestRunner(FHDLTestCase):
 100     def __init__(self, test_data):
 101         super().__init__("run_all")
 102         self.test_data = test_data
 103
 104     def run_all(self):
 105         m = Module()
 106         comb = m.d.comb
 107         instruction = Signal(32)
 108
 109         pdecode = create_pdecode()
 110
 111         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 112
 113         pspec = SPRPipeSpec(id_wid=2)
 114         m.submodules.alu = alu = SPRBasePipe(pspec)
 115
 116         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 117         comb += alu.p.valid_i.eq(1)
 118         comb += alu.n.ready_i.eq(1)
 119         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 120         sim = Simulator(m)
 121
 122         sim.add_clock(1e-6)
 123         def process():
 124             for test in self.test_data:
 125                 print(test.name)
 126                 program = test.program
 127                 self.subTest(test.name)
 128                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 129                                 test.mem, test.msr)
 130                 gen = program.generate_instructions()
 131                 instructions = list(zip(gen, program.assembly.splitlines()))
 132
 133                 pc = sim.pc.CIA.value
 134                 index = pc//4
 135                 while index < len(instructions):
 136                     ins, code = instructions[index]
 137
 138                     print("pc %08x instr: %08x" % (pc, ins & 0xffffffff))
 139                     print(code)
 140                     if 'XER' in sim.spr:
 141                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 142                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 143                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 144                         print ("before: so/ov/32", so, ov, ov32)
 145
 146                     # ask the decoder to decode this binary data (endian'd)
 147                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 148                     yield instruction.eq(ins)          # raw binary instr.
 149                     yield Settle()
 150                     fn_unit = yield pdecode2.e.fn_unit
 151                     self.assertEqual(fn_unit, Function.SPR.value)
 152                     yield from set_alu_inputs(alu, pdecode2, sim)
 153                     yield
 154                     opname = code.split(' ')[0]
 155                     yield from sim.call(opname)
 156                     pc = sim.pc.CIA.value
 157                     index = pc//4
 158                     print("pc after %08x" % (pc))
 159
 160                     vld = yield alu.n.valid_o
 161                     while not vld:
 162                         yield
 163                         vld = yield alu.n.valid_o
 164                     yield
 165
 166                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 167
 168         sim.add_sync_process(process)
 169         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
 170                             traces=[]):
 171             sim.run()
 172
 173     def check_alu_outputs(self, alu, dec2, sim, code):
 174
 175         rc = yield dec2.e.rc.data
 176         cridx_ok = yield dec2.e.write_cr.ok
 177         cridx = yield dec2.e.write_cr.data
 178
 179         print ("check extra output", repr(code), cridx_ok, cridx)
 180         if rc:
 181             self.assertEqual(cridx, 0, code)
 182
 183         sim_o = {}
 184         res = {}
 185
 186         yield from ALUHelpers.get_int_o(res, alu, dec2)
 187         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
 188         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 189         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 190         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 191
 192         print ("output", res)
 193
 194         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 195         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 196         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 197         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 198         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
 199
 200         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 201         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 202         ALUHelpers.check_int_o(self, res, sim_o, code)
 203         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
 204         ALUHelpers.check_xer_so(self, res, sim_o, code)
 205
 206
 207 if __name__ == "__main__":
 208     unittest.main(exit=False)
 209     suite = unittest.TestSuite()
 210     suite.addTest(TestRunner(SPRTestCase.test_data))
 211
 212     runner = unittest.TextTestRunner()
 213     runner.run(suite)