src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 import inspect
   7 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
   8 from soc.regfile.util import fast_reg_to_spr  # HACK!
   9 from soc.regfile.regfiles import FastRegs
  10
  11 class TestAccumulatorBase:
  12
  13     def __init__(self):
  14         self.test_data = []
  15         # automatically identifies anything starting with "case_" and
  16         # runs it.  very similar to unittest auto-identification except
  17         # we need a different system
  18         for n, v in self.__class__.__dict__.items():
  19             if n.startswith("case_") and callable(v):
  20                 v(self)
  21
  22     def add_case(self, prog, initial_regs=None, initial_sprs=None,
  23                         initial_cr=0, initial_msr=0,
  24                         initial_mem=None):
  25
  26         test_name = inspect.stack()[1][3] # name of caller of this function
  27         tc = TestCase(prog, test_name,
  28                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
  29                       msr=initial_msr,
  30                       mem=initial_mem)
  31
  32         self.test_data.append(tc)
  33
  34
  35 class TestCase:
  36     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  37                  msr=0,
  38                  do_sim=True,
  39                  extra_break_addr=None):
  40
  41         self.program = program
  42         self.name = name
  43
  44         if regs is None:
  45             regs = [0] * 32
  46         if sprs is None:
  47             sprs = {}
  48         if mem is None:
  49             mem = {}
  50         self.regs = regs
  51         self.sprs = sprs
  52         self.cr = cr
  53         self.mem = mem
  54         self.msr = msr
  55         self.do_sim = do_sim
  56         self.extra_break_addr = extra_break_addr
  57
  58
  59 class ALUHelpers:
  60
  61     def get_sim_fast_reg(res, sim, dec2, reg, name):
  62         spr_sel = fast_reg_to_spr(reg)
  63         spr_data = sim.spr[spr_sel].value
  64         res[name] = spr_data
  65
  66     def get_sim_cia(res, sim, dec2):
  67         res['cia'] = sim.pc.CIA.value
  68
  69     # use this *after* the simulation has run a step (it returns CIA)
  70     def get_sim_nia(res, sim, dec2):
  71         res['nia'] = sim.pc.CIA.value
  72
  73     def get_sim_msr(res, sim, dec2):
  74         res['msr'] = sim.msr.value
  75
  76     def get_sim_slow_spr1(res, sim, dec2):
  77         spr1_en = yield dec2.e.read_spr1.ok
  78         if spr1_en:
  79             spr1_sel = yield dec2.e.read_spr1.data
  80             spr1_data = sim.spr[spr1_sel].value
  81             res['spr1'] = spr1_data
  82
  83     def get_sim_fast_spr1(res, sim, dec2):
  84         fast1_en = yield dec2.e.read_fast1.ok
  85         if fast1_en:
  86             fast1_sel = yield dec2.e.read_fast1.data
  87             spr1_sel = fast_reg_to_spr(fast1_sel)
  88             spr1_data = sim.spr[spr1_sel].value
  89             res['fast1'] = spr1_data
  90
  91     def get_sim_fast_spr2(res, sim, dec2):
  92         fast2_en = yield dec2.e.read_fast2.ok
  93         if fast2_en:
  94             fast2_sel = yield dec2.e.read_fast2.data
  95             spr2_sel = fast_reg_to_spr(fast2_sel)
  96             spr2_data = sim.spr[spr2_sel].value
  97             res['fast2'] = spr2_data
  98
  99     def get_sim_cr_a(res, sim, dec2):
 100         cridx_ok = yield dec2.e.read_cr1.ok
 101         if cridx_ok:
 102             cridx = yield dec2.e.read_cr1.data
 103             res['cr_a'] = sim.crl[cridx].get_range().value
 104
 105     def get_sim_int_ra(res, sim, dec2):
 106         # TODO: immediate RA zero
 107         reg1_ok = yield dec2.e.read_reg1.ok
 108         if reg1_ok:
 109             data1 = yield dec2.e.read_reg1.data
 110             res['ra'] = sim.gpr(data1).value
 111
 112     def get_sim_int_rb(res, sim, dec2):
 113         reg2_ok = yield dec2.e.read_reg2.ok
 114         if reg2_ok:
 115             data = yield dec2.e.read_reg2.data
 116             res['rb'] = sim.gpr(data).value
 117
 118     def get_sim_int_rc(res, sim, dec2):
 119         reg3_ok = yield dec2.e.read_reg3.ok
 120         if reg3_ok:
 121             data = yield dec2.e.read_reg3.data
 122             res['rc'] = sim.gpr(data).value
 123
 124     def get_rd_sim_xer_ca(res, sim, dec2):
 125         cry_in = yield dec2.e.do.input_carry
 126         xer_in = yield dec2.e.xer_in
 127         if xer_in or cry_in == CryIn.CA.value:
 128             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 129             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 130             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 131
 132     def set_int_ra(alu, dec2, inp):
 133         # TODO: immediate RA zero.
 134         if 'ra' in inp:
 135             yield alu.p.data_i.ra.eq(inp['ra'])
 136         else:
 137             yield alu.p.data_i.ra.eq(0)
 138
 139     def set_int_rb(alu, dec2, inp):
 140         yield alu.p.data_i.rb.eq(0)
 141         if 'rb' in inp:
 142             yield alu.p.data_i.rb.eq(inp['rb'])
 143         # If there's an immediate, set the B operand to that
 144         imm_ok = yield dec2.e.do.imm_data.imm_ok
 145         if imm_ok:
 146             data2 = yield dec2.e.do.imm_data.imm
 147             yield alu.p.data_i.rb.eq(data2)
 148
 149     def set_int_rc(alu, dec2, inp):
 150         if 'rc' in inp:
 151             yield alu.p.data_i.rc.eq(inp['rc'])
 152         else:
 153             yield alu.p.data_i.rc.eq(0)
 154
 155     def set_xer_ca(alu, dec2, inp):
 156         if 'xer_ca' in inp:
 157             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 158             print("extra inputs: CA/32", bin(inp['xer_ca']))
 159
 160     def set_xer_ov(alu, dec2, inp):
 161         if 'xer_ov' in inp:
 162             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 163             print("extra inputs: OV/32", bin(inp['xer_ov']))
 164
 165     def set_xer_so(alu, dec2, inp):
 166         if 'xer_so' in inp:
 167             so = inp['xer_so']
 168             print("extra inputs: so", so)
 169             yield alu.p.data_i.xer_so.eq(so)
 170
 171     def set_msr(alu, dec2, inp):
 172         print("TODO: deprecate set_msr")
 173         if 'msr' in inp:
 174             yield alu.p.data_i.msr.eq(inp['msr'])
 175
 176     def set_cia(alu, dec2, inp):
 177         print("TODO: deprecate set_cia")
 178         if 'cia' in inp:
 179             yield alu.p.data_i.cia.eq(inp['cia'])
 180
 181     def set_slow_spr1(alu, dec2, inp):
 182         if 'spr1' in inp:
 183             yield alu.p.data_i.spr1.eq(inp['spr1'])
 184
 185     def set_slow_spr2(alu, dec2, inp):
 186         if 'spr2' in inp:
 187             yield alu.p.data_i.spr2.eq(inp['spr2'])
 188
 189     def set_fast_spr1(alu, dec2, inp):
 190         if 'fast1' in inp:
 191             yield alu.p.data_i.fast1.eq(inp['fast1'])
 192
 193     def set_fast_spr2(alu, dec2, inp):
 194         if 'fast2' in inp:
 195             yield alu.p.data_i.fast2.eq(inp['fast2'])
 196
 197     def set_cr_a(alu, dec2, inp):
 198         if 'cr_a' in inp:
 199             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 200
 201     def set_cr_b(alu, dec2, inp):
 202         if 'cr_b' in inp:
 203             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 204
 205     def set_cr_c(alu, dec2, inp):
 206         if 'cr_c' in inp:
 207             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 208
 209     def set_full_cr(alu, dec2, inp):
 210         if 'full_cr' in inp:
 211             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 212         else:
 213             yield alu.p.data_i.full_cr.eq(0)
 214
 215     def get_slow_spr1(res, alu, dec2):
 216         spr1_valid = yield alu.n.data_o.spr1.ok
 217         if spr1_valid:
 218             res['spr1'] = yield alu.n.data_o.spr1.data
 219
 220     def get_slow_spr2(res, alu, dec2):
 221         spr2_valid = yield alu.n.data_o.spr2.ok
 222         if spr2_valid:
 223             res['spr2'] = yield alu.n.data_o.spr2.data
 224
 225     def get_fast_spr1(res, alu, dec2):
 226         spr1_valid = yield alu.n.data_o.fast1.ok
 227         if spr1_valid:
 228             res['fast1'] = yield alu.n.data_o.fast1.data
 229
 230     def get_fast_spr2(res, alu, dec2):
 231         spr2_valid = yield alu.n.data_o.fast2.ok
 232         if spr2_valid:
 233             res['fast2'] = yield alu.n.data_o.fast2.data
 234
 235     def get_cia(res, alu, dec2):
 236         res['cia'] = yield alu.p.data_i.cia
 237
 238     def get_nia(res, alu, dec2):
 239         nia_valid = yield alu.n.data_o.nia.ok
 240         if nia_valid:
 241             res['nia'] = yield alu.n.data_o.nia.data
 242
 243     def get_msr(res, alu, dec2):
 244         msr_valid = yield alu.n.data_o.msr.ok
 245         if msr_valid:
 246             res['msr'] = yield alu.n.data_o.msr.data
 247
 248     def get_int_o1(res, alu, dec2):
 249         out_reg_valid = yield dec2.e.write_ea.ok
 250         if out_reg_valid:
 251             res['o1'] = yield alu.n.data_o.o1.data
 252
 253     def get_int_o(res, alu, dec2):
 254         out_reg_valid = yield dec2.e.write_reg.ok
 255         if out_reg_valid:
 256             res['o'] = yield alu.n.data_o.o.data
 257
 258     def get_cr_a(res, alu, dec2):
 259         cridx_ok = yield dec2.e.write_cr.ok
 260         if cridx_ok:
 261             res['cr_a'] = yield alu.n.data_o.cr0.data
 262
 263     def get_xer_so(res, alu, dec2):
 264         oe = yield dec2.e.do.oe.oe
 265         oe_ok = yield dec2.e.do.oe.ok
 266         xer_out = yield dec2.e.xer_out
 267         if not (yield alu.n.data_o.xer_so.ok):
 268             return
 269         if xer_out or (oe and oe_ok):
 270             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 271
 272     def get_xer_ov(res, alu, dec2):
 273         oe = yield dec2.e.do.oe.oe
 274         oe_ok = yield dec2.e.do.oe.ok
 275         xer_out = yield dec2.e.xer_out
 276         if not (yield alu.n.data_o.xer_ov.ok):
 277             return
 278         if xer_out or (oe and oe_ok):
 279             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 280
 281     def get_xer_ca(res, alu, dec2):
 282         cry_out = yield dec2.e.do.output_carry
 283         xer_out = yield dec2.e.xer_out
 284         if not (yield alu.n.data_o.xer_ca.ok):
 285             return
 286         if xer_out or (cry_out):
 287             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 288
 289     def get_sim_int_o(res, sim, dec2):
 290         out_reg_valid = yield dec2.e.write_reg.ok
 291         if out_reg_valid:
 292             write_reg_idx = yield dec2.e.write_reg.data
 293             res['o'] = sim.gpr(write_reg_idx).value
 294
 295     def get_sim_int_o1(res, sim, dec2):
 296         out_reg_valid = yield dec2.e.write_ea.ok
 297         if out_reg_valid:
 298             write_reg_idx = yield dec2.e.write_ea.data
 299             res['o1'] = sim.gpr(write_reg_idx).value
 300
 301     def get_wr_sim_cr_a(res, sim, dec2):
 302         cridx_ok = yield dec2.e.write_cr.ok
 303         if cridx_ok:
 304             cridx = yield dec2.e.write_cr.data
 305             res['cr_a'] = sim.crl[cridx].get_range().value
 306
 307     def get_wr_fast_spr2(res, sim, dec2):
 308         ok = yield dec2.e.write_fast2.ok
 309         if ok:
 310             spr_num = yield dec2.e.write_fast2.data
 311             spr_num = fast_reg_to_spr(spr_num)
 312             spr_name = spr_dict[spr_num].SPR
 313             res['fast2'] = sim.spr[spr_name].value
 314
 315     def get_wr_fast_spr1(res, sim, dec2):
 316         ok = yield dec2.e.write_fast1.ok
 317         if ok:
 318             spr_num = yield dec2.e.write_fast1.data
 319             spr_num = fast_reg_to_spr(spr_num)
 320             spr_name = spr_dict[spr_num].SPR
 321             res['fast1'] = sim.spr[spr_name].value
 322
 323     def get_wr_slow_spr1(res, sim, dec2):
 324         ok = yield dec2.e.write_spr.ok
 325         if ok:
 326             spr_num = yield dec2.e.write_spr.data
 327             spr_name = spr_dict[spr_num].SPR
 328             res['spr1'] = sim.spr[spr_name].value
 329
 330     def get_wr_sim_xer_ca(res, sim, dec2):
 331         # if not (yield alu.n.data_o.xer_ca.ok):
 332         #    return
 333         cry_out = yield dec2.e.do.output_carry
 334         xer_out = yield dec2.e.xer_out
 335         if cry_out or xer_out:
 336             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 337             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 338             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 339
 340     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 341         oe = yield dec2.e.do.oe.oe
 342         oe_ok = yield dec2.e.do.oe.ok
 343         xer_out = yield dec2.e.xer_out
 344         print("get_wr_sim_xer_ov", xer_out)
 345         if not (yield alu.n.data_o.xer_ov.ok):
 346             return
 347         if xer_out or (oe and oe_ok):
 348             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 349             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 350             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 351
 352     def get_wr_sim_xer_so(res, sim, alu, dec2):
 353         oe = yield dec2.e.do.oe.oe
 354         oe_ok = yield dec2.e.do.oe.ok
 355         xer_out = yield dec2.e.xer_out
 356         if not (yield alu.n.data_o.xer_so.ok):
 357             return
 358         if xer_out or (oe and oe_ok):
 359             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 360
 361     def get_sim_xer_ov(res, sim, dec2):
 362         oe = yield dec2.e.do.oe.oe
 363         oe_ok = yield dec2.e.do.oe.ok
 364         xer_in = yield dec2.e.xer_in
 365         print("get_sim_xer_ov", xer_in)
 366         if xer_in or (oe and oe_ok):
 367             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 368             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 369             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 370
 371     def get_sim_xer_so(res, sim, dec2):
 372         oe = yield dec2.e.do.oe.oe
 373         oe_ok = yield dec2.e.do.oe.ok
 374         xer_in = yield dec2.e.xer_in
 375         if xer_in or (oe and oe_ok):
 376             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 377
 378     def check_slow_spr1(dut, res, sim_o, msg):
 379         if 'spr1' in res:
 380             expected = sim_o['spr1']
 381             alu_out = res['spr1']
 382             print(f"expected {expected:x}, actual: {alu_out:x}")
 383             dut.assertEqual(expected, alu_out, msg)
 384
 385     def check_fast_spr1(dut, res, sim_o, msg):
 386         if 'fast1' in res:
 387             expected = sim_o['fast1']
 388             alu_out = res['fast1']
 389             print(f"expected {expected:x}, actual: {alu_out:x}")
 390             dut.assertEqual(expected, alu_out, msg)
 391
 392     def check_fast_spr2(dut, res, sim_o, msg):
 393         if 'fast2' in res:
 394             expected = sim_o['fast2']
 395             alu_out = res['fast2']
 396             print(f"expected {expected:x}, actual: {alu_out:x}")
 397             dut.assertEqual(expected, alu_out, msg)
 398
 399     def check_int_o1(dut, res, sim_o, msg):
 400         if 'o1' in res:
 401             expected = sim_o['o1']
 402             alu_out = res['o1']
 403             print(f"expected {expected:x}, actual: {alu_out:x}")
 404             dut.assertEqual(expected, alu_out, msg)
 405
 406     def check_int_o(dut, res, sim_o, msg):
 407         if 'o' in res:
 408             expected = sim_o['o']
 409             alu_out = res['o']
 410             print(f"expected int sim {expected:x}, actual: {alu_out:x}")
 411             dut.assertEqual(expected, alu_out, msg)
 412
 413     def check_msr(dut, res, sim_o, msg):
 414         if 'msr' in res:
 415             expected = sim_o['msr']
 416             alu_out = res['msr']
 417             print(f"expected {expected:x}, actual: {alu_out:x}")
 418             dut.assertEqual(expected, alu_out, msg)
 419
 420     def check_nia(dut, res, sim_o, msg):
 421         if 'nia' in res:
 422             expected = sim_o['nia']
 423             alu_out = res['nia']
 424             print(f"expected {expected:x}, actual: {alu_out:x}")
 425             dut.assertEqual(expected, alu_out, msg)
 426
 427     def check_cr_a(dut, res, sim_o, msg):
 428         if 'cr_a' in res:
 429             cr_expected = sim_o['cr_a']
 430             cr_actual = res['cr_a']
 431             print("CR", cr_expected, cr_actual)
 432             dut.assertEqual(cr_expected, cr_actual, msg)
 433
 434     def check_xer_ca(dut, res, sim_o, msg):
 435         if 'xer_ca' in res:
 436             ca_expected = sim_o['xer_ca']
 437             ca_actual = res['xer_ca']
 438             print("CA", ca_expected, ca_actual)
 439             dut.assertEqual(ca_expected, ca_actual, msg)
 440
 441     def check_xer_ov(dut, res, sim_o, msg):
 442         if 'xer_ov' in res:
 443             ov_expected = sim_o['xer_ov']
 444             ov_actual = res['xer_ov']
 445             print("OV", ov_expected, ov_actual)
 446             dut.assertEqual(ov_expected, ov_actual, msg)
 447
 448     def check_xer_so(dut, res, sim_o, msg):
 449         if 'xer_so' in res:
 450             so_expected = sim_o['xer_so']
 451             so_actual = res['xer_so']
 452             print("SO", so_expected, so_actual)
 453             dut.assertEqual(so_expected, so_actual, msg)