src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8 from soc.regfile.regfiles import FastRegs
   9
  10
  11 class TestCase:
  12     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  13                        msr=0):
  14
  15         self.program = program
  16         self.name = name
  17
  18         if regs is None:
  19             regs = [0] * 32
  20         if sprs is None:
  21             sprs = {}
  22         if mem is None:
  23             mem = {}
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.cr = cr
  27         self.mem = mem
  28         self.msr = msr
  29
  30 class ALUHelpers:
  31
  32     def get_sim_fast_reg(res, sim, dec2, reg, name):
  33         spr_sel = fast_reg_to_spr(reg)
  34         spr_data = sim.spr[spr_sel].value
  35         res[name] = spr_data
  36
  37     def get_sim_cia(res, sim, dec2):
  38         res['cia'] = sim.pc.CIA.value
  39
  40     # use this *after* the simulation has run a step (it returns CIA)
  41     def get_sim_nia(res, sim, dec2):
  42         res['nia'] = sim.pc.CIA.value
  43
  44     def get_sim_msr(res, sim, dec2):
  45         res['msr'] = sim.msr.value
  46
  47     def get_sim_fast_spr1(res, sim, dec2):
  48         fast1_en = yield dec2.e.read_fast1.ok
  49         if fast1_en:
  50             fast1_sel = yield dec2.e.read_fast1.data
  51             spr1_sel = fast_reg_to_spr(fast1_sel)
  52             spr1_data = sim.spr[spr1_sel].value
  53             res['fast1'] = spr1_data
  54
  55     def get_sim_fast_spr2(res, sim, dec2):
  56         fast2_en = yield dec2.e.read_fast2.ok
  57         if fast2_en:
  58             fast2_sel = yield dec2.e.read_fast2.data
  59             spr2_sel = fast_reg_to_spr(fast2_sel)
  60             spr2_data = sim.spr[spr2_sel].value
  61             res['fast2'] = spr2_data
  62
  63     def get_sim_cr_a(res, sim, dec2):
  64         cridx_ok = yield dec2.e.read_cr1.ok
  65         if cridx_ok:
  66             cridx = yield dec2.e.read_cr1.data
  67             res['cr_a'] = sim.crl[cridx].get_range().value
  68
  69     def get_sim_int_ra(res, sim, dec2):
  70         # TODO: immediate RA zero
  71         reg1_ok = yield dec2.e.read_reg1.ok
  72         if reg1_ok:
  73             data1 = yield dec2.e.read_reg1.data
  74             res['ra'] = sim.gpr(data1).value
  75
  76     def get_sim_int_rb(res, sim, dec2):
  77         reg2_ok = yield dec2.e.read_reg2.ok
  78         if reg2_ok:
  79             data = yield dec2.e.read_reg2.data
  80             res['rb'] = sim.gpr(data).value
  81
  82     def get_sim_int_rc(res, sim, dec2):
  83         reg3_ok = yield dec2.e.read_reg3.ok
  84         if reg3_ok:
  85             data = yield dec2.e.read_reg3.data
  86             res['rc'] = sim.gpr(data).value
  87
  88     def get_rd_sim_xer_ca(res, sim, dec2):
  89         cry_in = yield dec2.e.input_carry
  90         if cry_in == CryIn.CA.value:
  91             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  92             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  93             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
  94
  95     def set_int_ra(alu, dec2, inp):
  96         # TODO: immediate RA zero.
  97         if 'ra' in inp:
  98             yield alu.p.data_i.ra.eq(inp['ra'])
  99         else:
 100             yield alu.p.data_i.ra.eq(0)
 101
 102     def set_int_rb(alu, dec2, inp):
 103         yield alu.p.data_i.rb.eq(0)
 104         if 'rb' in inp:
 105             yield alu.p.data_i.rb.eq(inp['rb'])
 106         # If there's an immediate, set the B operand to that
 107         imm_ok = yield dec2.e.imm_data.imm_ok
 108         if imm_ok:
 109             data2 = yield dec2.e.imm_data.imm
 110             yield alu.p.data_i.rb.eq(data2)
 111
 112     def set_int_rc(alu, dec2, inp):
 113         if 'rc' in inp:
 114             yield alu.p.data_i.rc.eq(inp['rc'])
 115         else:
 116             yield alu.p.data_i.rc.eq(0)
 117
 118     def set_xer_ca(alu, dec2, inp):
 119         if 'xer_ca' in inp:
 120             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 121             print ("extra inputs: CA/32", bin(inp['xer_ca']))
 122
 123     def set_xer_ov(alu, dec2, inp):
 124         if 'xer_ov' in inp:
 125             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 126             print ("extra inputs: OV/32", bin(inp['xer_ov']))
 127
 128     def set_xer_so(alu, dec2, inp):
 129         if 'xer_so' in inp:
 130             so = inp['xer_so']
 131             print ("extra inputs: so", so)
 132             yield alu.p.data_i.xer_so.eq(so)
 133
 134     def set_msr(alu, dec2, inp):
 135         if 'msr' in inp:
 136             yield alu.p.data_i.msr.eq(inp['msr'])
 137
 138     def set_cia(alu, dec2, inp):
 139         if 'cia' in inp:
 140             yield alu.p.data_i.cia.eq(inp['cia'])
 141
 142     def set_slow_spr1(alu, dec2, inp):
 143         if 'spr1' in inp:
 144             yield alu.p.data_i.spr1.eq(inp['spr1'])
 145
 146     def set_slow_spr2(alu, dec2, inp):
 147         if 'spr2' in inp:
 148             yield alu.p.data_i.spr2.eq(inp['spr2'])
 149
 150     def set_fast_spr1(alu, dec2, inp):
 151         if 'fast1' in inp:
 152             yield alu.p.data_i.fast1.eq(inp['fast1'])
 153
 154     def set_fast_spr2(alu, dec2, inp):
 155         if 'fast2' in inp:
 156             yield alu.p.data_i.fast2.eq(inp['fast2'])
 157
 158     def set_cr_a(alu, dec2, inp):
 159         if 'cr_a' in inp:
 160             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 161
 162     def set_cr_b(alu, dec2, inp):
 163         if 'cr_b' in inp:
 164             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 165
 166     def set_cr_c(alu, dec2, inp):
 167         if 'cr_c' in inp:
 168             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 169
 170     def set_full_cr(alu, dec2, inp):
 171         if 'full_cr' in inp:
 172             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 173         else:
 174             yield alu.p.data_i.full_cr.eq(0)
 175
 176     def get_slow_spr1(res, alu, dec2):
 177         spr1_valid = yield alu.n.data_o.spr1.ok
 178         if spr1_valid:
 179             res['spr1'] = yield alu.n.data_o.spr1.data
 180
 181     def get_slow_spr2(res, alu, dec2):
 182         spr2_valid = yield alu.n.data_o.spr2.ok
 183         if spr2_valid:
 184             res['spr2'] = yield alu.n.data_o.spr2.data
 185
 186     def get_fast_spr1(res, alu, dec2):
 187         spr1_valid = yield alu.n.data_o.fast1.ok
 188         if spr1_valid:
 189             res['fast1'] = yield alu.n.data_o.fast1.data
 190
 191     def get_fast_spr2(res, alu, dec2):
 192         spr2_valid = yield alu.n.data_o.fast2.ok
 193         if spr2_valid:
 194             res['fast2'] = yield alu.n.data_o.fast2.data
 195
 196     def get_cia(res, alu, dec2):
 197         res['cia'] = yield alu.p.data_i.cia
 198
 199     def get_nia(res, alu, dec2):
 200         nia_valid = yield alu.n.data_o.nia.ok
 201         if nia_valid:
 202             res['nia'] = yield alu.n.data_o.nia.data
 203
 204     def get_msr(res, alu, dec2):
 205         msr_valid = yield alu.n.data_o.msr.ok
 206         if msr_valid:
 207             res['msr'] = yield alu.n.data_o.msr.data
 208
 209     def get_int_o1(res, alu, dec2):
 210         out_reg_valid = yield dec2.e.write_ea.ok
 211         if out_reg_valid:
 212             res['o1'] = yield alu.n.data_o.o1.data
 213
 214     def get_int_o(res, alu, dec2):
 215         out_reg_valid = yield dec2.e.write_reg.ok
 216         if out_reg_valid:
 217             res['o'] = yield alu.n.data_o.o.data
 218
 219     def get_cr_a(res, alu, dec2):
 220         cridx_ok = yield dec2.e.write_cr.ok
 221         if cridx_ok:
 222             res['cr_a'] = yield alu.n.data_o.cr0.data
 223
 224     def get_xer_so(res, alu, dec2):
 225         oe = yield dec2.e.oe.oe
 226         oe_ok = yield dec2.e.oe.ok
 227         if oe and oe_ok:
 228             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 229
 230     def get_xer_ov(res, alu, dec2):
 231         oe = yield dec2.e.oe.oe
 232         oe_ok = yield dec2.e.oe.ok
 233         if oe and oe_ok:
 234             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 235
 236     def get_xer_ca(res, alu, dec2):
 237         cry_out = yield dec2.e.output_carry
 238         if cry_out:
 239             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 240
 241     def get_sim_int_o(res, sim, dec2):
 242         out_reg_valid = yield dec2.e.write_reg.ok
 243         if out_reg_valid:
 244             write_reg_idx = yield dec2.e.write_reg.data
 245             res['o'] = sim.gpr(write_reg_idx).value
 246
 247     def get_sim_int_o1(res, sim, dec2):
 248         out_reg_valid = yield dec2.e.write_ea.ok
 249         if out_reg_valid:
 250             write_reg_idx = yield dec2.e.write_ea.data
 251             res['o1'] = sim.gpr(write_reg_idx).value
 252
 253     def get_wr_sim_cr_a(res, sim, dec2):
 254         cridx_ok = yield dec2.e.write_cr.ok
 255         if cridx_ok:
 256             cridx = yield dec2.e.write_cr.data
 257             res['cr_a'] = sim.crl[cridx].get_range().value
 258
 259     def get_wr_fast_spr2(res, sim, dec2):
 260         ok = yield dec2.e.write_fast2.ok
 261         if ok:
 262             spr_num = yield dec2.e.write_fast2.data
 263             spr_num = fast_reg_to_spr(spr_num)
 264             spr_name = spr_dict[spr_num].SPR
 265             res['fast2'] = sim.spr[spr_name].value
 266
 267     def get_wr_fast_spr1(res, sim, dec2):
 268         ok = yield dec2.e.write_fast1.ok
 269         if ok:
 270             spr_num = yield dec2.e.write_fast1.data
 271             spr_num = fast_reg_to_spr(spr_num)
 272             spr_name = spr_dict[spr_num].SPR
 273             res['fast1'] = sim.spr[spr_name].value
 274
 275     def get_wr_sim_xer_ca(res, sim, dec2):
 276         cry_out = yield dec2.e.output_carry
 277         if cry_out:
 278             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 279             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 280             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 281
 282     def get_sim_xer_ov(res, sim, dec2):
 283         oe = yield dec2.e.oe.oe
 284         oe_ok = yield dec2.e.oe.ok
 285         if oe and oe_ok:
 286             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 287             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 288             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 289
 290     def get_sim_xer_so(res, sim, dec2):
 291         oe = yield dec2.e.oe.oe
 292         oe_ok = yield dec2.e.oe.ok
 293         if oe and oe_ok:
 294             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 295
 296     def check_fast_spr1(dut, res, sim_o, msg):
 297         if 'fast1' in res:
 298             expected = sim_o['fast1']
 299             alu_out = res['fast1']
 300             print(f"expected {expected:x}, actual: {alu_out:x}")
 301             dut.assertEqual(expected, alu_out, msg)
 302
 303     def check_fast_spr2(dut, res, sim_o, msg):
 304         if 'fast2' in res:
 305             expected = sim_o['fast2']
 306             alu_out = res['fast2']
 307             print(f"expected {expected:x}, actual: {alu_out:x}")
 308             dut.assertEqual(expected, alu_out, msg)
 309
 310     def check_int_o1(dut, res, sim_o, msg):
 311         if 'o1' in res:
 312             expected = sim_o['o1']
 313             alu_out = res['o1']
 314             print(f"expected {expected:x}, actual: {alu_out:x}")
 315             dut.assertEqual(expected, alu_out, msg)
 316
 317     def check_int_o(dut, res, sim_o, msg):
 318         if 'o' in res:
 319             expected = sim_o['o']
 320             alu_out = res['o']
 321             print(f"expected {expected:x}, actual: {alu_out:x}")
 322             dut.assertEqual(expected, alu_out, msg)
 323
 324     def check_nia(dut, res, sim_o, msg):
 325         if 'nia' in res:
 326             expected = sim_o['nia']
 327             alu_out = res['nia']
 328             print(f"expected {expected:x}, actual: {alu_out:x}")
 329             dut.assertEqual(expected, alu_out, msg)
 330
 331     def check_cr_a(dut, res, sim_o, msg):
 332         if 'cr_a' in res:
 333             cr_expected = sim_o['cr_a']
 334             cr_actual = res['cr_a']
 335             print ("CR", cr_expected, cr_actual)
 336             dut.assertEqual(cr_expected, cr_actual, msg)
 337
 338     def check_xer_ca(dut, res, sim_o, msg):
 339         if 'xer_ca' in res:
 340             ca_expected = sim_o['xer_ca']
 341             ca_actual = res['xer_ca']
 342             print ("CA", ca_expected, ca_actual)
 343             dut.assertEqual(ca_expected, ca_actual, msg)
 344
 345     def check_xer_ov(dut, res, sim_o, msg):
 346         if 'xer_ov' in res:
 347             ov_expected = sim_o['xer_ov']
 348             ov_actual = res['xer_ov']
 349             print ("OV", ov_expected, ov_actual)
 350             dut.assertEqual(ov_expected, ov_actual, msg)
 351
 352     def check_xer_so(dut, res, sim_o, msg):
 353         if 'xer_so' in res:
 354             so_expected = sim_o['xer_so']
 355             so_actual = res['xer_so']
 356             print ("SO", so_expected, so_actual)
 357             dut.assertEqual(so_expected, so_actual, msg)
 358