src/soc/fu/test/common.py

   1 from soc.decoder.power_enums import XER_bits
   2
   3
   4 class TestCase:
   5     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
   6                        msr=0):
   7
   8         self.program = program
   9         self.name = name
  10
  11         if regs is None:
  12             regs = [0] * 32
  13         if sprs is None:
  14             sprs = {}
  15         if mem is None:
  16             mem = {}
  17         self.regs = regs
  18         self.sprs = sprs
  19         self.cr = cr
  20         self.mem = mem
  21         self.msr = msr
  22
  23 class ALUHelpers:
  24
  25     def get_sim_int_ra(res, sim, dec2):
  26         reg1_ok = yield dec2.e.read_reg1.ok
  27         if reg1_ok:
  28             data1 = yield dec2.e.read_reg1.data
  29             res['ra'] = sim.gpr(data1).value
  30
  31     def get_sim_int_rb(res, sim, dec2):
  32         reg2_ok = yield dec2.e.read_reg2.ok
  33         if reg2_ok:
  34             data = yield dec2.e.read_reg2.data
  35             res['rb'] = sim.gpr(data).value
  36
  37     def set_int_ra(alu, dec2, inp):
  38         if 'ra' in inp:
  39             yield alu.p.data_i.ra.eq(inp['ra'])
  40         else:
  41             yield alu.p.data_i.ra.eq(0)
  42
  43     def set_int_rb(alu, dec2, inp):
  44         yield alu.p.data_i.rb.eq(0)
  45         if 'rb' in inp:
  46             yield alu.p.data_i.rb.eq(inp['rb'])
  47         # If there's an immediate, set the B operand to that
  48         imm_ok = yield dec2.e.imm_data.imm_ok
  49         if imm_ok:
  50             data2 = yield dec2.e.imm_data.imm
  51             yield alu.p.data_i.rb.eq(data2)
  52
  53     def set_int_rc(alu, dec2, inp):
  54         if 'rc' in inp:
  55             yield alu.p.data_i.rc.eq(inp['rc'])
  56         else:
  57             yield alu.p.data_i.rc.eq(0)
  58
  59     def set_xer_ca(alu, dec2, inp):
  60         if 'xer_ca' in inp:
  61             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
  62             print ("extra inputs: CA/32", bin(inp['xer_ca']))
  63
  64     def set_xer_so(alu, dec2, inp):
  65         if 'xer_so' in inp:
  66             so = inp['xer_so']
  67             print ("extra inputs: so", so)
  68             yield alu.p.data_i.xer_so.eq(so)
  69
  70     def set_fast_cia(alu, dec2, inp):
  71         if 'cia' in inp:
  72             yield alu.p.data_i.cia.eq(inp['cia'])
  73
  74     def set_fast_spr1(alu, dec2, inp):
  75         if 'spr1' in inp:
  76             yield alu.p.data_i.spr1.eq(inp['spr1'])
  77
  78     def set_fast_spr2(alu, dec2, inp):
  79         if 'spr2' in inp:
  80             yield alu.p.data_i.spr2.eq(inp['spr2'])
  81
  82     def set_cr_a(alu, dec2, inp):
  83         if 'cr_a' in inp:
  84             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
  85
  86     def set_cr_b(alu, dec2, inp):
  87         if 'cr_b' in inp:
  88             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
  89
  90     def set_cr_c(alu, dec2, inp):
  91         if 'cr_c' in inp:
  92             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
  93
  94     def set_full_cr(alu, dec2, inp):
  95         if 'full_cr' in inp:
  96             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
  97         else:
  98             yield alu.p.data_i.full_cr.eq(0)
  99
 100     def get_int_o(res, alu, dec2):
 101         out_reg_valid = yield dec2.e.write_reg.ok
 102         if out_reg_valid:
 103             res['o'] = yield alu.n.data_o.o.data
 104
 105     def get_cr_a(res, alu, dec2):
 106         cridx_ok = yield dec2.e.write_cr.ok
 107         if cridx_ok:
 108             res['cr_a'] = yield alu.n.data_o.cr0.data
 109
 110     def get_xer_so(res, alu, dec2):
 111         oe = yield dec2.e.oe.oe
 112         oe_ok = yield dec2.e.oe.ok
 113         if oe and oe_ok:
 114             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 115
 116     def get_xer_ov(res, alu, dec2):
 117         oe = yield dec2.e.oe.oe
 118         oe_ok = yield dec2.e.oe.ok
 119         if oe and oe_ok:
 120             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 121
 122     def get_xer_ca(res, alu, dec2):
 123         cry_out = yield dec2.e.output_carry
 124         if cry_out:
 125             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 126
 127     def get_sim_int_o(res, sim, dec2):
 128         out_reg_valid = yield dec2.e.write_reg.ok
 129         if out_reg_valid:
 130             write_reg_idx = yield dec2.e.write_reg.data
 131             res['o'] = sim.gpr(write_reg_idx).value
 132
 133     def get_sim_cr_a(res, sim, dec2):
 134         cridx_ok = yield dec2.e.write_cr.ok
 135         if cridx_ok:
 136             cridx = yield dec2.e.write_cr.data
 137             res['cr_a'] = sim.crl[cridx].get_range().value
 138
 139     def get_sim_xer_ca(res, sim, dec2):
 140         cry_out = yield dec2.e.output_carry
 141         if cry_out:
 142             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 143             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 144             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 145
 146     def get_sim_xer_ov(res, sim, dec2):
 147         oe = yield dec2.e.oe.oe
 148         oe_ok = yield dec2.e.oe.ok
 149         if oe and oe_ok:
 150             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 151             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 152             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 153
 154     def get_sim_xer_so(res, sim, dec2):
 155         oe = yield dec2.e.oe.oe
 156         oe_ok = yield dec2.e.oe.ok
 157         if oe and oe_ok:
 158             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 159
 160     def check_int_o(dut, res, sim_o, msg):
 161         if 'o' in res:
 162             expected = sim_o['o']
 163             alu_out = res['o']
 164             print(f"expected {expected:x}, actual: {alu_out:x}")
 165             dut.assertEqual(expected, alu_out, msg)
 166
 167     def check_cr_a(dut, res, sim_o, msg):
 168         if 'cr_a' in res:
 169             cr_expected = sim_o['cr_a']
 170             cr_actual = res['cr_a']
 171             print ("CR", cr_expected, cr_actual)
 172             dut.assertEqual(cr_expected, cr_actual, msg)
 173
 174     def check_xer_ca(dut, res, sim_o, msg):
 175         if 'xer_ca' in res:
 176             ca_expected = sim_o['xer_ca']
 177             ca_actual = res['xer_ca']
 178             print ("CA", ca_expected, ca_actual)
 179             dut.assertEqual(ca_expected, ca_actual, msg)
 180
 181     def check_xer_ov(dut, res, sim_o, msg):
 182         if 'xer_ov' in res:
 183             ov_expected = sim_o['xer_ov']
 184             ov_actual = res['xer_ov']
 185             print ("OV", ov_expected, ov_actual)
 186             dut.assertEqual(ov_expected, ov_actual, msg)
 187
 188     def check_xer_so(dut, res, sim_o, msg):
 189         if 'xer_so' in res:
 190             so_expected = sim_o['xer_so']
 191             so_actual = res['xer_so']
 192             print ("SO", so_expected, so_actual)
 193             dut.assertEqual(so_expected, so_actual, msg)
 194