src/soc/fu/test/common.py

   1 """
   2 Bugreports:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=361
   4 """
   5
   6 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
   7 from soc.regfile.util import fast_reg_to_spr # HACK!
   8 from soc.regfile.regfiles import FastRegs
   9
  10
  11 class TestCase:
  12     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
  13                        msr=0):
  14
  15         self.program = program
  16         self.name = name
  17
  18         if regs is None:
  19             regs = [0] * 32
  20         if sprs is None:
  21             sprs = {}
  22         if mem is None:
  23             mem = {}
  24         self.regs = regs
  25         self.sprs = sprs
  26         self.cr = cr
  27         self.mem = mem
  28         self.msr = msr
  29
  30 class ALUHelpers:
  31
  32     def get_sim_fast_reg(res, sim, dec2, reg, name):
  33         spr_sel = fast_reg_to_spr(reg)
  34         spr_data = sim.spr[spr_sel].value
  35         res[name] = spr_data
  36
  37     def get_sim_cia(res, sim, dec2):
  38         res['cia'] = sim.pc.CIA.value
  39
  40     # use this *after* the simulation has run a step (it returns CIA)
  41     def get_sim_nia(res, sim, dec2):
  42         res['nia'] = sim.pc.CIA.value
  43
  44     def get_sim_msr(res, sim, dec2):
  45         res['msr'] = sim.msr.value
  46
  47     def get_sim_slow_spr1(res, sim, dec2):
  48         spr1_en = yield dec2.e.read_spr1.ok
  49         if spr1_en:
  50             spr1_sel = yield dec2.e.read_spr1.data
  51             spr1_data = sim.spr[spr1_sel].value
  52             res['spr1'] = spr1_data
  53
  54     def get_sim_fast_spr1(res, sim, dec2):
  55         fast1_en = yield dec2.e.read_fast1.ok
  56         if fast1_en:
  57             fast1_sel = yield dec2.e.read_fast1.data
  58             spr1_sel = fast_reg_to_spr(fast1_sel)
  59             spr1_data = sim.spr[spr1_sel].value
  60             res['fast1'] = spr1_data
  61
  62     def get_sim_fast_spr2(res, sim, dec2):
  63         fast2_en = yield dec2.e.read_fast2.ok
  64         if fast2_en:
  65             fast2_sel = yield dec2.e.read_fast2.data
  66             spr2_sel = fast_reg_to_spr(fast2_sel)
  67             spr2_data = sim.spr[spr2_sel].value
  68             res['fast2'] = spr2_data
  69
  70     def get_sim_cr_a(res, sim, dec2):
  71         cridx_ok = yield dec2.e.read_cr1.ok
  72         if cridx_ok:
  73             cridx = yield dec2.e.read_cr1.data
  74             res['cr_a'] = sim.crl[cridx].get_range().value
  75
  76     def get_sim_int_ra(res, sim, dec2):
  77         # TODO: immediate RA zero
  78         reg1_ok = yield dec2.e.read_reg1.ok
  79         if reg1_ok:
  80             data1 = yield dec2.e.read_reg1.data
  81             res['ra'] = sim.gpr(data1).value
  82
  83     def get_sim_int_rb(res, sim, dec2):
  84         reg2_ok = yield dec2.e.read_reg2.ok
  85         if reg2_ok:
  86             data = yield dec2.e.read_reg2.data
  87             res['rb'] = sim.gpr(data).value
  88
  89     def get_sim_int_rc(res, sim, dec2):
  90         reg3_ok = yield dec2.e.read_reg3.ok
  91         if reg3_ok:
  92             data = yield dec2.e.read_reg3.data
  93             res['rc'] = sim.gpr(data).value
  94
  95     def get_rd_sim_xer_ca(res, sim, dec2):
  96         cry_in = yield dec2.e.do.input_carry
  97         xer_in = yield dec2.e.xer_in
  98         if xer_in or cry_in == CryIn.CA.value:
  99             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 100             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 101             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 102
 103     def set_int_ra(alu, dec2, inp):
 104         # TODO: immediate RA zero.
 105         if 'ra' in inp:
 106             yield alu.p.data_i.ra.eq(inp['ra'])
 107         else:
 108             yield alu.p.data_i.ra.eq(0)
 109
 110     def set_int_rb(alu, dec2, inp):
 111         yield alu.p.data_i.rb.eq(0)
 112         if 'rb' in inp:
 113             yield alu.p.data_i.rb.eq(inp['rb'])
 114         # If there's an immediate, set the B operand to that
 115         imm_ok = yield dec2.e.do.imm_data.imm_ok
 116         if imm_ok:
 117             data2 = yield dec2.e.do.imm_data.imm
 118             yield alu.p.data_i.rb.eq(data2)
 119
 120     def set_int_rc(alu, dec2, inp):
 121         if 'rc' in inp:
 122             yield alu.p.data_i.rc.eq(inp['rc'])
 123         else:
 124             yield alu.p.data_i.rc.eq(0)
 125
 126     def set_xer_ca(alu, dec2, inp):
 127         if 'xer_ca' in inp:
 128             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
 129             print ("extra inputs: CA/32", bin(inp['xer_ca']))
 130
 131     def set_xer_ov(alu, dec2, inp):
 132         if 'xer_ov' in inp:
 133             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
 134             print ("extra inputs: OV/32", bin(inp['xer_ov']))
 135
 136     def set_xer_so(alu, dec2, inp):
 137         if 'xer_so' in inp:
 138             so = inp['xer_so']
 139             print ("extra inputs: so", so)
 140             yield alu.p.data_i.xer_so.eq(so)
 141
 142     def set_msr(alu, dec2, inp):
 143         if 'msr' in inp:
 144             yield alu.p.data_i.msr.eq(inp['msr'])
 145
 146     def set_cia(alu, dec2, inp):
 147         if 'cia' in inp:
 148             yield alu.p.data_i.cia.eq(inp['cia'])
 149
 150     def set_slow_spr1(alu, dec2, inp):
 151         if 'spr1' in inp:
 152             yield alu.p.data_i.spr1.eq(inp['spr1'])
 153
 154     def set_slow_spr2(alu, dec2, inp):
 155         if 'spr2' in inp:
 156             yield alu.p.data_i.spr2.eq(inp['spr2'])
 157
 158     def set_fast_spr1(alu, dec2, inp):
 159         if 'fast1' in inp:
 160             yield alu.p.data_i.fast1.eq(inp['fast1'])
 161
 162     def set_fast_spr2(alu, dec2, inp):
 163         if 'fast2' in inp:
 164             yield alu.p.data_i.fast2.eq(inp['fast2'])
 165
 166     def set_cr_a(alu, dec2, inp):
 167         if 'cr_a' in inp:
 168             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
 169
 170     def set_cr_b(alu, dec2, inp):
 171         if 'cr_b' in inp:
 172             yield alu.p.data_i.cr_b.eq(inp['cr_b'])
 173
 174     def set_cr_c(alu, dec2, inp):
 175         if 'cr_c' in inp:
 176             yield alu.p.data_i.cr_c.eq(inp['cr_c'])
 177
 178     def set_full_cr(alu, dec2, inp):
 179         if 'full_cr' in inp:
 180             yield alu.p.data_i.full_cr.eq(inp['full_cr'])
 181         else:
 182             yield alu.p.data_i.full_cr.eq(0)
 183
 184     def get_slow_spr1(res, alu, dec2):
 185         spr1_valid = yield alu.n.data_o.spr1.ok
 186         if spr1_valid:
 187             res['spr1'] = yield alu.n.data_o.spr1.data
 188
 189     def get_slow_spr2(res, alu, dec2):
 190         spr2_valid = yield alu.n.data_o.spr2.ok
 191         if spr2_valid:
 192             res['spr2'] = yield alu.n.data_o.spr2.data
 193
 194     def get_fast_spr1(res, alu, dec2):
 195         spr1_valid = yield alu.n.data_o.fast1.ok
 196         if spr1_valid:
 197             res['fast1'] = yield alu.n.data_o.fast1.data
 198
 199     def get_fast_spr2(res, alu, dec2):
 200         spr2_valid = yield alu.n.data_o.fast2.ok
 201         if spr2_valid:
 202             res['fast2'] = yield alu.n.data_o.fast2.data
 203
 204     def get_cia(res, alu, dec2):
 205         res['cia'] = yield alu.p.data_i.cia
 206
 207     def get_nia(res, alu, dec2):
 208         nia_valid = yield alu.n.data_o.nia.ok
 209         if nia_valid:
 210             res['nia'] = yield alu.n.data_o.nia.data
 211
 212     def get_msr(res, alu, dec2):
 213         msr_valid = yield alu.n.data_o.msr.ok
 214         if msr_valid:
 215             res['msr'] = yield alu.n.data_o.msr.data
 216
 217     def get_int_o1(res, alu, dec2):
 218         out_reg_valid = yield dec2.e.write_ea.ok
 219         if out_reg_valid:
 220             res['o1'] = yield alu.n.data_o.o1.data
 221
 222     def get_int_o(res, alu, dec2):
 223         out_reg_valid = yield dec2.e.write_reg.ok
 224         if out_reg_valid:
 225             res['o'] = yield alu.n.data_o.o.data
 226
 227     def get_cr_a(res, alu, dec2):
 228         cridx_ok = yield dec2.e.write_cr.ok
 229         if cridx_ok:
 230             res['cr_a'] = yield alu.n.data_o.cr0.data
 231
 232     def get_xer_so(res, alu, dec2):
 233         oe = yield dec2.e.do.oe.oe
 234         oe_ok = yield dec2.e.do.oe.ok
 235         xer_out = yield dec2.e.xer_out
 236         if not (yield alu.n.data_o.xer_so.ok):
 237             return
 238         if xer_out or (oe and oe_ok):
 239             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 240
 241     def get_xer_ov(res, alu, dec2):
 242         oe = yield dec2.e.do.oe.oe
 243         oe_ok = yield dec2.e.do.oe.ok
 244         xer_out = yield dec2.e.xer_out
 245         if not (yield alu.n.data_o.xer_ov.ok):
 246             return
 247         if xer_out or (oe and oe_ok):
 248             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 249
 250     def get_xer_ca(res, alu, dec2):
 251         cry_out = yield dec2.e.do.output_carry
 252         xer_out = yield dec2.e.xer_out
 253         if not (yield alu.n.data_o.xer_ca.ok):
 254             return
 255         if xer_out or (cry_out):
 256             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 257
 258     def get_sim_int_o(res, sim, dec2):
 259         out_reg_valid = yield dec2.e.write_reg.ok
 260         if out_reg_valid:
 261             write_reg_idx = yield dec2.e.write_reg.data
 262             res['o'] = sim.gpr(write_reg_idx).value
 263
 264     def get_sim_int_o1(res, sim, dec2):
 265         out_reg_valid = yield dec2.e.write_ea.ok
 266         if out_reg_valid:
 267             write_reg_idx = yield dec2.e.write_ea.data
 268             res['o1'] = sim.gpr(write_reg_idx).value
 269
 270     def get_wr_sim_cr_a(res, sim, dec2):
 271         cridx_ok = yield dec2.e.write_cr.ok
 272         if cridx_ok:
 273             cridx = yield dec2.e.write_cr.data
 274             res['cr_a'] = sim.crl[cridx].get_range().value
 275
 276     def get_wr_fast_spr2(res, sim, dec2):
 277         ok = yield dec2.e.write_fast2.ok
 278         if ok:
 279             spr_num = yield dec2.e.write_fast2.data
 280             spr_num = fast_reg_to_spr(spr_num)
 281             spr_name = spr_dict[spr_num].SPR
 282             res['fast2'] = sim.spr[spr_name].value
 283
 284     def get_wr_fast_spr1(res, sim, dec2):
 285         ok = yield dec2.e.write_fast1.ok
 286         if ok:
 287             spr_num = yield dec2.e.write_fast1.data
 288             spr_num = fast_reg_to_spr(spr_num)
 289             spr_name = spr_dict[spr_num].SPR
 290             res['fast1'] = sim.spr[spr_name].value
 291
 292     def get_wr_slow_spr1(res, sim, dec2):
 293         ok = yield dec2.e.write_spr.ok
 294         if ok:
 295             spr_num = yield dec2.e.write_spr.data
 296             spr_name = spr_dict[spr_num].SPR
 297             res['spr1'] = sim.spr[spr_name].value
 298
 299     def get_wr_sim_xer_ca(res, sim, dec2):
 300         #if not (yield alu.n.data_o.xer_ca.ok):
 301         #    return
 302         cry_out = yield dec2.e.do.output_carry
 303         xer_out = yield dec2.e.xer_out
 304         if cry_out or xer_out:
 305             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 306             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
 307             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 308
 309     def get_wr_sim_xer_ov(res, sim, alu, dec2):
 310         oe = yield dec2.e.do.oe.oe
 311         oe_ok = yield dec2.e.do.oe.ok
 312         xer_out = yield dec2.e.xer_out
 313         print ("get_wr_sim_xer_ov", xer_out)
 314         if not (yield alu.n.data_o.xer_ov.ok):
 315             return
 316         if xer_out or (oe and oe_ok):
 317             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 318             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 319             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 320
 321     def get_wr_sim_xer_so(res, sim, alu, dec2):
 322         oe = yield dec2.e.do.oe.oe
 323         oe_ok = yield dec2.e.do.oe.ok
 324         xer_out = yield dec2.e.xer_out
 325         if not (yield alu.n.data_o.xer_so.ok):
 326             return
 327         if xer_out or (oe and oe_ok):
 328             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 329
 330     def get_sim_xer_ov(res, sim, dec2):
 331         oe = yield dec2.e.do.oe.oe
 332         oe_ok = yield dec2.e.do.oe.ok
 333         xer_in = yield dec2.e.xer_in
 334         print ("get_sim_xer_ov", xer_in)
 335         if xer_in or (oe and oe_ok):
 336             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 337             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 338             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 339
 340     def get_sim_xer_so(res, sim, dec2):
 341         oe = yield dec2.e.do.oe.oe
 342         oe_ok = yield dec2.e.do.oe.ok
 343         xer_in = yield dec2.e.xer_in
 344         if xer_in or (oe and oe_ok):
 345             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 346
 347     def check_slow_spr1(dut, res, sim_o, msg):
 348         if 'spr1' in res:
 349             expected = sim_o['spr1']
 350             alu_out = res['spr1']
 351             print(f"expected {expected:x}, actual: {alu_out:x}")
 352             dut.assertEqual(expected, alu_out, msg)
 353
 354     def check_fast_spr1(dut, res, sim_o, msg):
 355         if 'fast1' in res:
 356             expected = sim_o['fast1']
 357             alu_out = res['fast1']
 358             print(f"expected {expected:x}, actual: {alu_out:x}")
 359             dut.assertEqual(expected, alu_out, msg)
 360
 361     def check_fast_spr2(dut, res, sim_o, msg):
 362         if 'fast2' in res:
 363             expected = sim_o['fast2']
 364             alu_out = res['fast2']
 365             print(f"expected {expected:x}, actual: {alu_out:x}")
 366             dut.assertEqual(expected, alu_out, msg)
 367
 368     def check_int_o1(dut, res, sim_o, msg):
 369         if 'o1' in res:
 370             expected = sim_o['o1']
 371             alu_out = res['o1']
 372             print(f"expected {expected:x}, actual: {alu_out:x}")
 373             dut.assertEqual(expected, alu_out, msg)
 374
 375     def check_int_o(dut, res, sim_o, msg):
 376         if 'o' in res:
 377             expected = sim_o['o']
 378             alu_out = res['o']
 379             print(f"expected {expected:x}, actual: {alu_out:x}")
 380             dut.assertEqual(expected, alu_out, msg)
 381
 382     def check_msr(dut, res, sim_o, msg):
 383         if 'msr' in res:
 384             expected = sim_o['msr']
 385             alu_out = res['msr']
 386             print(f"expected {expected:x}, actual: {alu_out:x}")
 387             dut.assertEqual(expected, alu_out, msg)
 388
 389     def check_nia(dut, res, sim_o, msg):
 390         if 'nia' in res:
 391             expected = sim_o['nia']
 392             alu_out = res['nia']
 393             print(f"expected {expected:x}, actual: {alu_out:x}")
 394             dut.assertEqual(expected, alu_out, msg)
 395
 396     def check_cr_a(dut, res, sim_o, msg):
 397         if 'cr_a' in res:
 398             cr_expected = sim_o['cr_a']
 399             cr_actual = res['cr_a']
 400             print ("CR", cr_expected, cr_actual)
 401             dut.assertEqual(cr_expected, cr_actual, msg)
 402
 403     def check_xer_ca(dut, res, sim_o, msg):
 404         if 'xer_ca' in res:
 405             ca_expected = sim_o['xer_ca']
 406             ca_actual = res['xer_ca']
 407             print ("CA", ca_expected, ca_actual)
 408             dut.assertEqual(ca_expected, ca_actual, msg)
 409
 410     def check_xer_ov(dut, res, sim_o, msg):
 411         if 'xer_ov' in res:
 412             ov_expected = sim_o['xer_ov']
 413             ov_actual = res['xer_ov']
 414             print ("OV", ov_expected, ov_actual)
 415             dut.assertEqual(ov_expected, ov_actual, msg)
 416
 417     def check_xer_so(dut, res, sim_o, msg):
 418         if 'xer_so' in res:
 419             so_expected = sim_o['xer_so']
 420             so_actual = res['xer_so']
 421             print ("SO", so_expected, so_actual)
 422             dut.assertEqual(so_expected, so_actual, msg)
 423