1 # Proof of correctness for trap pipeline, main stage
6 * https://bugs.libre-soc.org/show_bug.cgi?id=421
12 from nmigen
import Cat
, Const
, Elaboratable
, Module
, Signal
13 from nmigen
.asserts
import Assert
, AnyConst
14 from nmigen
.cli
import rtlil
16 from nmutil
.formaltest
import FHDLTestCase
18 from soc
.consts
import MSR
20 from soc
.decoder
.power_enums
import MicrOp
22 from soc
.fu
.trap
.main_stage
import TrapMainStage
23 from soc
.fu
.trap
.pipe_data
import TrapPipeSpec
24 from soc
.fu
.trap
.trap_input_record
import CompTrapOpSubset
27 def field(r
, start
, end
):
28 return r
[63-end
:63-start
]
31 class Driver(Elaboratable
):
35 def elaborate(self
, platform
):
39 rec
= CompTrapOpSubset()
40 pspec
= TrapPipeSpec(id_wid
=2)
42 m
.submodules
.dut
= dut
= TrapMainStage(pspec
)
44 # frequently used aliases
46 msr_o
, msr_i
= dut
.o
.msr
, dut
.i
.msr
52 with m
.Switch(op
.insn_type
):
53 with m
.Case(MicrOp
.OP_SC
):
55 Assert(dut
.o
.srr0
.ok
),
56 Assert(dut
.o
.srr1
.ok
),
58 Assert(dut
.o
.srr0
.data
== (dut
.i
.cia
+ 4)[0:64]),
59 Assert(field(dut
.o
.srr1
, 33, 36) == 0),
60 Assert(field(dut
.o
.srr1
, 42, 47) == 0),
61 Assert(field(dut
.o
.srr1
, 0, 32) == field(msr_i
, 0, 32)),
62 Assert(field(dut
.o
.srr1
, 37, 41) == field(msr_i
, 37, 41)),
63 Assert(field(dut
.o
.srr1
, 48, 63) == field(msr_i
, 48, 63)),
65 with m
.Case(MicrOp
.OP_RFID
):
70 Assert(msr_o
[MSR
.HV
] == (srr1_i
[MSR
.HV
] & msr_i
[MSR
.HV
])),
71 Assert(msr_o
[MSR
.EE
] == (srr1_i
[MSR
.EE
] | srr1_i
[MSR
.PR
])),
72 Assert(msr_o
[MSR
.IR
] == (srr1_i
[MSR
.IR
] | srr1_i
[MSR
.PR
])),
73 Assert(msr_o
[MSR
.DR
] == (srr1_i
[MSR
.DR
] | srr1_i
[MSR
.PR
])),
74 Assert(field(msr_o
, 0, 2) == field(srr1_i
, 0, 2)),
75 Assert(field(msr_o
, 4, 28) == field(srr1_i
, 4, 28)),
76 Assert(msr_o
[63-32] == srr1_i
[63-32]),
77 Assert(field(msr_o
, 37, 41) == field(srr1_i
, 37, 41)),
78 Assert(field(msr_o
, 49, 50) == field(srr1_i
, 49, 50)),
79 Assert(field(msr_o
, 52, 57) == field(srr1_i
, 52, 57)),
80 Assert(field(msr_o
, 60, 63) == field(srr1_i
, 60, 63)),
81 Assert(dut
.o
.nia
.data
== Cat(Const(0, 2), dut
.i
.srr0
[2:])),
83 with m
.If(msr_i
[MSR
.HV
]):
84 comb
+= Assert(msr_o
[MSR
.ME
] == srr1_i
[MSR
.ME
])
86 comb
+= Assert(msr_o
[MSR
.ME
] == msr_i
[MSR
.ME
])
87 with m
.If((field(msr_i
, 29, 31) != 0b010) |
88 (field(msr_i
, 29, 31) != 0b000)):
89 comb
+= Assert(field(msr_o
.data
, 29, 31) == field(srr1_i
, 29, 31))
91 comb
+= dut
.i
.ctx
.matches(dut
.o
.ctx
)
96 class TrapMainStageTestCase(FHDLTestCase
):
97 def test_formal(self
):
98 self
.assertFormal(Driver(), mode
="bmc", depth
=10)
99 self
.assertFormal(Driver(), mode
="cover", depth
=10)
101 def test_ilang(self
):
102 vl
= rtlil
.convert(Driver(), ports
=[])
103 with
open("trap_main_stage.il", "w") as f
:
107 if __name__
== '__main__':