src/soc/fu/trap/main_stage.py

   1
   2 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)
   3 from nmutil.pipemodbase import PipeModBase
   4 from nmutil.clz import CLZ
   5 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
   6 from soc.decoder.power_enums import InternalOp
   7
   8 from soc.decoder.power_fields import DecodeFields
   9 from soc.decoder.power_fieldsn import SignalBitRange
  10
  11
  12 def array_of(count, bitwidth):
  13     res = []
  14     for i in range(count):
  15         res.append(Signal(bitwidth, reset_less=True))
  16     return res
  17
  18
  19 class LogicalMainStage(PipeModBase):
  20     def __init__(self, pspec):
  21         super().__init__(pspec, "main")
  22         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  23         self.fields.create_specs()
  24
  25     def ispec(self):
  26         return TrapInputData(self.pspec)
  27
  28     def ospec(self):
  29         return TrapOutputData(self.pspec)
  30
  31     def elaborate(self, platform):
  32         m = Module()
  33         comb = m.d.comb
  34         op = self.i.ctx.op
  35
  36         # take copy of D-Form TO field
  37         i_fields = self.fields.FormD
  38         to = Signal(i_fields.TO[0:-1].shape())
  39         comb += to.eq(i_fields.TO[0:-1])
  40
  41         # signed/unsigned temporaries for RA and RB
  42         a_s = Signal(signed(64), reset_less=True)
  43         b_s = Signal(signed(64), reset_less=True)
  44
  45         a = Signal(64, reset_less=True)
  46         b = Signal(64, reset_less=True)
  47
  48         # set up A and B comparison (truncate/sign-extend if 32 bit)
  49         with m.If(op.is_32bit):
  50             comb += a_s.eq(self.i.a[0:32], Repl(self.i.a[32], 32))
  51             comb += b_s.eq(self.i.b[0:32], Repl(self.i.b[32], 32))
  52             comb += a.eq(self.i.a[0:32])
  53             comb += b.eq(self.i.b[0:32])
  54         with m.Else():
  55             comb += a_s.eq(self.i.a)
  56             comb += b_s.eq(self.i.b)
  57             comb += a.eq(self.i.a)
  58             comb += b.eq(self.i.b)
  59
  60         # establish comparison bits
  61         lt_s = Signal(reset_less=True)
  62         gt_s = Signal(reset_less=True)
  63         lt_u = Signal(reset_less=True)
  64         gt_u = Signal(reset_less=True)
  65         equal = Signal(reset_less=True)
  66
  67         comb += lt_s.eq(a_s < b_s)
  68         comb += gt_s.eq(a_s > b_s)
  69         comb += lt_u.eq(a < b)
  70         comb += gt_u.eq(a > b)
  71         comb += equal.eq(a == b)
  72
  73         # They're in reverse bit order because POWER. Check Book 1,
  74         # Appendix C.6 for chart
  75         trap_bits = Signal(5)
  76         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  77
  78         # establish if the trap should go ahead (any tests requested in TO)
  79         should_trap = Signal()
  80         comb += should_trap.eq((trap_bits & to).any())
  81
  82         # TODO: some #defines for the bits n stuff.
  83         with m.Switch(op):
  84             with m.Case(InternalOp.OP_TRAP):
  85                 with m.If(should_trap):
  86                     comb += self.o.nia.data.eq(0x700)         # trap address
  87                     comb += self.o.nia.ok.eq(1)
  88                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
  89                     comb += self.o.srr1[63-46].eq(1)     # XXX which bit?
  90                     comb += self.o.srr1.ok.eq(1)
  91                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
  92                     comb += self.o.srr0.ok.eq(1)
  93
  94         comb += self.o.ctx.eq(self.i.ctx)
  95
  96         return m