src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.fu.branch.main_stage import br_ext
  13 from soc.decoder.power_enums import InternalOp
  14
  15 from soc.decoder.power_fields import DecodeFields
  16 from soc.decoder.power_fieldsn import SignalBitRange
  17
  18 from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR)
  19
  20 # Listed in V3.0B Book III Chap 4.2.1
  21 # MSR bit numbers
  22 MSR_SF  = (63 - 0)     # Sixty-Four bit mode
  23 MSR_HV  = (63 - 3)     # Hypervisor state
  24 MSR_S   = (63 - 41)    # Secure state
  25 MSR_EE  = (63 - 48)    # External interrupt Enable
  26 MSR_PR  = (63 - 49)    # PRoblem state
  27 MSR_FP  = (63 - 50)    # FP available
  28 MSR_ME  = (63 - 51)    # Machine Check int enable
  29 MSR_IR  = (63 - 58)    # Instruction Relocation
  30 MSR_DR  = (63 - 59)    # Data Relocation
  31 MSR_PMM = (63 - 60)    # Performance Monitor Mark
  32 MSR_RI  = (63 - 62)    # Recoverable Interrupt
  33 MSR_LE  = (63 - 63)    # Little Endian
  34
  35 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  36
  37 # note that these correspond to trap_input_record.traptype bits 0,1,2,3
  38 # (TODO: add more?)
  39
  40 PI_FP   = (63 - 43)    # 1 if FP exception
  41 PI_PRIV = (63 - 45)    # 1 if privileged interrupt
  42 PI_TRAP = (63 - 46)    # 1 if exception is "trap" type
  43 PI_ADR  = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
  44
  45
  46 def msr_copy(msr_o, msr_i, zero_me=True):
  47     """
  48     -- ISA says this:
  49     --  Defined MSR bits are classified as either full func-
  50     --  tion or partial function. Full function MSR bits are
  51     --  saved in SRR1 or HSRR1 when an interrupt other
  52     --  than a System Call Vectored interrupt occurs and
  53     --  restored by rfscv, rfid, or hrfid, while partial func-
  54     --  tion MSR bits are not saved or restored.
  55     --  Full function MSR bits lie in the range 0:32, 37:41, and
  56     --  48:63, and partial function MSR bits lie in the range
  57     --  33:36 and 42:47. (Note this is IBM bit numbering).
  58     msr_out := (others => '0');
  59     msr_out(63 downto 31) := msr(63 downto 31);
  60     msr_out(26 downto 22) := msr(26 downto 22);
  61     msr_out(15 downto 0)  := msr(15 downto 0);
  62     """
  63     l = []
  64     if zero_me:
  65         l.append(msr_o.eq(0))
  66     for stt, end in [(0,16), (22, 27), (31, 64)]:
  67         l.append(msr_o[stt:end].eq(msr_i[stt:end]))
  68     return l
  69
  70
  71 def msr_check_pr(m, msr):
  72     """msr_check_pr: checks "problem state"
  73     """
  74     comb = m.d.comb
  75     with m.If(msr[MSR_PR]):
  76         comb += msr[MSR_EE].eq(1) # set external interrupt bit
  77         comb += msr[MSR_IR].eq(1) # set instruction relocation bit
  78         comb += msr[MSR_DR].eq(1) # set data relocation bit
  79
  80
  81 class TrapMainStage(PipeModBase):
  82     def __init__(self, pspec):
  83         super().__init__(pspec, "main")
  84         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  85         self.fields.create_specs()
  86
  87     def trap(self, m, return_addr, trap_addr):
  88         """trap """ # TODO add descriptive docstring
  89         comb  = m.d.comb
  90         msr_i = self.i.msr
  91         nia_o, srr0_o, srr1_o = self.o.nia, self.o.srr0, self.o.srr1
  92
  93         # trap address
  94         comb += nia_o.data.eq(trap_addr)
  95         comb += nia_o.ok.eq(1)
  96
  97         # addr to begin from on return
  98         comb += srr0_o.data.eq(return_addr)
  99         comb += srr0_o.ok.eq(1)
 100
 101         # take a copy of the current MSR in SRR1
 102         comb += msr_copy(srr1_o.data, msr_i) # old MSR
 103         comb += srr1_o.ok.eq(1)
 104
 105     def ispec(self):
 106         return TrapInputData(self.pspec)
 107
 108     def ospec(self):
 109         return TrapOutputData(self.pspec)
 110
 111     def elaborate(self, platform):
 112         m = Module()
 113         comb = m.d.comb
 114         op = self.i.ctx.op
 115
 116         # convenience variables
 117         a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
 118         o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
 119         srr0_o, srr1_o = self.o.srr0, self.o.srr1
 120         traptype, trapaddr = op.traptype, op.trapaddr
 121
 122         # take copy of D-Form TO field
 123         i_fields = self.fields.FormD
 124         to = Signal(i_fields.TO[0:-1].shape())
 125         comb += to.eq(i_fields.TO[0:-1])
 126
 127         # signed/unsigned temporaries for RA and RB
 128         a_s = Signal(signed(64), reset_less=True)
 129         b_s = Signal(signed(64), reset_less=True)
 130
 131         a = Signal(64, reset_less=True)
 132         b = Signal(64, reset_less=True)
 133
 134         # set up A and B comparison (truncate/sign-extend if 32 bit)
 135         with m.If(op.is_32bit):
 136             comb += a_s.eq(exts(a_i, 32, 64))
 137             comb += b_s.eq(exts(b_i, 32, 64))
 138             comb += a.eq(a_i[0:32])
 139             comb += b.eq(b_i[0:32])
 140         with m.Else():
 141             comb += a_s.eq(a_i)
 142             comb += b_s.eq(b_i)
 143             comb += a.eq(a_i)
 144             comb += b.eq(b_i)
 145
 146         # establish comparison bits
 147         lt_s = Signal(reset_less=True)
 148         gt_s = Signal(reset_less=True)
 149         lt_u = Signal(reset_less=True)
 150         gt_u = Signal(reset_less=True)
 151         equal = Signal(reset_less=True)
 152
 153         comb += lt_s.eq(a_s < b_s)
 154         comb += gt_s.eq(a_s > b_s)
 155         comb += lt_u.eq(a < b)
 156         comb += gt_u.eq(a > b)
 157         comb += equal.eq(a == b)
 158
 159         # They're in reverse bit order because POWER.
 160         # Check V3.0B Book 1, Appendix C.6 for chart
 161         trap_bits = Signal(5, reset_less=True)
 162         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
 163
 164         # establish if the trap should go ahead (any tests requested in TO)
 165         # or if traptype is set already
 166         should_trap = Signal(reset_less=True)
 167         comb += should_trap.eq((trap_bits & to).any() | traptype.any())
 168
 169         # TODO: some #defines for the bits n stuff.
 170         with m.Switch(op):
 171             #### trap ####
 172             with m.Case(InternalOp.OP_TRAP):
 173                 # trap instructions (tw, twi, td, tdi)
 174                 with m.If(should_trap):
 175                     # generate trap-type program interrupt
 176                     self.trap(m, trapaddr<<4, cia_i)
 177                     with m.If(traptype == 0):
 178                         # say trap occurred (see 3.0B Book III 7.5.9)
 179                         comb += srr1_o.data[PI_TRAP].eq(1)
 180                     with m.If(traptype & TT_PRIV):
 181                         comb += srr1_o.data[PI_PRIV].eq(1)
 182                     with m.If(traptype & TT_FP):
 183                         comb += srr1_o.data[PI_FP].eq(1)
 184                     with m.If(traptype & TT_ADDR):
 185                         comb += srr1_o.data[PI_ADR].eq(1)
 186
 187             # move to MSR
 188             with m.Case(InternalOp.OP_MTMSR):
 189                 L = self.fields.FormX.L[0:-1] # X-Form field L
 190                 with m.If(L):
 191                     # just update EE and RI
 192                     comb += msr_o.data[MSR_EE].eq(a_i[MSR_EE])
 193                     comb += msr_o.data[MSR_RI].eq(a_i[MSR_RI])
 194                 with m.Else():
 195                     # Architecture says to leave out bits 3 (HV), 51 (ME)
 196                     # and 63 (LE) (IBM bit numbering)
 197                     for stt, end in [(1,12), (13, 60), (61, 64)]:
 198                         comb += msr_o.data[stt:end].eq(a_i[stt:end])
 199                     msr_check_pr(m, msr_o.data)
 200                 comb += msr_o.ok.eq(1)
 201
 202             # move from MSR
 203             with m.Case(InternalOp.OP_MFMSR):
 204                 # TODO: some of the bits need zeroing?  apparently not
 205                 comb += o.data.eq(msr_i)
 206                 comb += o.ok.eq(1)
 207
 208             with m.Case(InternalOp.OP_RFID):
 209                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 210                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 211
 212                 # return addr was in srr0
 213                 comb += nia_o.data.eq(br_ext(srr0_i[2:]))
 214                 comb += nia_o.ok.eq(1)
 215                 # MSR was in srr1
 216                 comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
 217                 msr_check_pr(m, msr_o.data)
 218                 comb += msr_o.ok.eq(1)
 219
 220             with m.Case(InternalOp.OP_SC):
 221                 # TODO: scv must generate illegal instruction.  this is
 222                 # the decoder's job, not ours, here.
 223
 224                 # jump to the trap address, return at cia+4
 225                 self.trap(m, 0xc00, cia_i+4)
 226
 227             # TODO (later)
 228             #with m.Case(InternalOp.OP_ADDPCIS):
 229             #    pass
 230
 231         comb += self.o.ctx.eq(self.i.ctx)
 232
 233         return m