src/soc/fu/trap/pipe_data.py

   1 from nmigen import Signal, Const
   2 from ieee754.fpcommon.getop import FPPipeContext
   3 from soc.fu.alu.pipe_data import IntegerData
   4
   5
   6 class TrapInputData(IntegerData):
   7     def __init__(self, pspec):
   8         super().__init__(pspec)
   9         self.a = Signal(64, reset_less=True)  # RA
  10         self.b = Signal(64, reset_less=True)  # RB/immediate
  11         self.cia = Signal(64, reset_less=True)  # Program counter
  12         self.msr = Signal(64, reset_less=True)  # MSR
  13
  14     def __iter__(self):
  15         yield from super().__iter__()
  16         yield self.a
  17         yield self.b
  18         yield self.cia
  19         yield self.msr
  20
  21     def eq(self, i):
  22         lst = super().eq(i)
  23         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  24                       self.cia.eq(i.nia), self.msr.eq(i.msr)]
  25
  26 class TrapOutputData(IntegerData):
  27     def __init__(self, pspec):
  28         super().__init__(pspec)
  29         self.nia = Signal(64, reset_less=True) # RA
  30         self.msr = Signal(64, reset_less=True) # RB/immediate
  31         self.srr0 = Signal(64, reset_less=True) # RB/immediate
  32         self.srr1 = Signal(64, reset_less=True) # RB/immediate
  33         self.should_trap = Signal(reset_less=True)
  34
  35     def __iter__(self):
  36         yield from super().__iter__()
  37         yield self.nia
  38         yield self.msr
  39         yield self.srr0
  40         yield self.srr1
  41         yield self.should_trap
  42
  43     def eq(self, i):
  44         lst = super().eq(i)
  45         return lst + [
  46             self.nia.eq(i.nia), self.msr.eq(i.msr),
  47             self.srr0.eq(i.srr0), self.srr1.eq(i.srr1),
  48             self.should_trap.eq(i.should_trap)]