3 from migen
import ClockSignal
, ResetSignal
, Signal
, Instance
, Cat
5 from litex
.soc
.interconnect
import wishbone
as wb
6 from litex
.soc
.cores
.cpu
import CPU
8 from soc
.config
.pinouts
import get_pinspecs
9 from soc
.debug
.jtag
import Pins
10 from c4m
.nmigen
.jtag
.tap
import IOType
12 from libresoc
.ls180
import io
13 from litex
.build
.generic_platform
import ConstraintManager
16 CPU_VARIANTS
= ["standard", "standard32", "standardjtag", "ls180"]
19 def make_wb_bus(prefix
, obj
, simple
=False):
21 outpins
= ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
23 outpins
+= ['cti', 'bte']
25 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
26 for i
in ['ack', 'err', 'dat_r']:
27 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
30 def make_wb_slave(prefix
, obj
):
32 for i
in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
33 res
['i_%s__%s' % (prefix
, i
)] = getattr(obj
, i
)
34 for o
in ['ack', 'err', 'dat_r']:
35 res
['o_%s__%s' % (prefix
, o
)] = getattr(obj
, o
)
38 def make_pad(res
, dirn
, name
, suffix
, cpup
, iop
):
39 cpud
, iod
= ('i', 'o') if dirn
else ('o', 'i')
40 res
['%s_%s__core__%s' % (cpud
, name
, suffix
)] = cpup
41 res
['%s_%s__pad__%s' % (iod
, name
, suffix
)] = iop
43 def get_field(rec
, name
):
47 return getattr(rec
, f
)
50 def make_jtag_ioconn(res
, pin
, cpupads
, iopads
):
51 (fn
, pin
, iotype
, pin_name
, scan_idx
) = pin
52 #serial_tx__core__o, serial_rx__pad__i,
53 # special-case sdram_clock
54 if pin
== 'clock' and fn
== 'sdr':
55 cpu
= cpupads
['sdram_clock']
56 io
= iopads
['sdram_clock']
60 print ("cpupads", cpupads
)
61 print ("iopads", iopads
)
62 print ("pin", fn
, pin
, iotype
, pin_name
)
65 name
= "%s_%s" % (fn
, pin
)
69 if iotype
in (IOType
.In
, IOType
.Out
):
71 if pin
== 'clock' and fn
== 'sdr':
74 elif len(ps
) == 2 and ps
[-1].isdigit():
77 cpup
= getattr(cpu
, pin
)[idx
]
78 iop
= getattr(io
, pin
)[idx
]
84 cpup
= getattr(cpu
, pin
)
85 iop
= getattr(io
, pin
)
87 if iotype
== IOType
.Out
:
88 # output from the pad is routed through C4M JTAG and so
89 # is an *INPUT* into core. ls180soc connects this to "real" peripheral
90 make_pad(res
, True, name
, "o", cpup
, iop
)
92 elif iotype
== IOType
.In
:
93 # input to the pad is routed through C4M JTAG and so
94 # is an *OUTPUT* into core. ls180soc connects this to "real" peripheral
95 make_pad(res
, False, name
, "i", cpup
, iop
)
97 elif iotype
== IOType
.InTriOut
:
98 if fn
== 'gpio': # sigh decode GPIO special-case
102 cpup
, iop
= get_field(cpu
, "i")[idx
], get_field(io
, "i")[idx
]
103 make_pad(res
, False, name
, "i", cpup
, iop
)
104 cpup
, iop
= get_field(cpu
, "o")[idx
], get_field(io
, "o")[idx
]
105 make_pad(res
, True, name
, "o", cpup
, iop
)
106 cpup
, iop
= get_field(cpu
, "oe")[idx
], get_field(io
, "oe")[idx
]
107 make_pad(res
, True, name
, "oe", cpup
, iop
)
109 if iotype
in (IOType
.In
, IOType
.InTriOut
):
110 sigs
.append(("i", 1))
111 if iotype
in (IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
):
112 sigs
.append(("o", 1))
113 if iotype
in (IOType
.TriOut
, IOType
.InTriOut
):
114 sigs
.append(("oe", 1))
119 human_name
= "Libre-SoC"
120 variants
= CPU_VARIANTS
121 endianness
= "little"
122 gcc_triple
= ("powerpc64le-linux", "powerpc64le-linux-gnu")
123 linker_output_format
= "elf64-powerpcle"
125 io_regions
= {0xc0000000: 0x10000000} # origin, length
129 return {"csr": 0xc0000000}
134 flags
+= "-mabi=elfv2 "
135 flags
+= "-msoft-float "
136 flags
+= "-mno-string "
137 flags
+= "-mno-multiple "
139 flags
+= "-mno-altivec "
140 flags
+= "-mlittle-endian "
141 flags
+= "-mstrict-align "
142 flags
+= "-fno-stack-protector "
143 flags
+= "-mcmodel=small "
144 flags
+= "-D__microwatt__ "
147 def __init__(self
, platform
, variant
="standard"):
148 self
.platform
= platform
149 self
.variant
= variant
150 self
.reset
= Signal()
151 self
.interrupt
= Signal(16)
153 if variant
== "standard32":
155 self
.dbus
= dbus
= wb
.Interface(data_width
=32, adr_width
=30)
157 self
.dbus
= dbus
= wb
.Interface(data_width
=64, adr_width
=29)
159 self
.ibus
= ibus
= wb
.Interface(data_width
=64, adr_width
=29)
161 self
.xics_icp
= icp
= wb
.Interface(data_width
=32, adr_width
=30)
162 self
.xics_ics
= ics
= wb
.Interface(data_width
=32, adr_width
=30)
164 jtag_en
= ('jtag' in variant
) or variant
== 'ls180'
166 if variant
!= "ls180":
167 self
.simple_gpio
= gpio
= wb
.Interface(data_width
=32, adr_width
=30)
169 self
.jtag_wb
= jtag_wb
= wb
.Interface(data_width
=64, adr_width
=29)
171 self
.periph_buses
= [ibus
, dbus
]
172 self
.memory_buses
= []
175 self
.periph_buses
.append(jtag_wb
)
176 self
.jtag_tck
= Signal(1)
177 self
.jtag_tms
= Signal(1)
178 self
.jtag_tdi
= Signal(1)
179 self
.jtag_tdo
= Signal(1)
181 self
.dmi_addr
= Signal(4)
182 self
.dmi_din
= Signal(64)
183 self
.dmi_dout
= Signal(64)
184 self
.dmi_wr
= Signal(1)
185 self
.dmi_ack
= Signal(1)
186 self
.dmi_req
= Signal(1)
190 self
.cpu_params
= dict(
192 i_clk
= ClockSignal(),
193 i_rst
= ResetSignal() | self
.reset
,
195 # Monitoring / Debugging
198 i_core_bigendian_i
= 0, # Signal(),
199 o_busy_o
= Signal(), # not connected
200 o_memerr_o
= Signal(), # not connected
201 o_pc_o
= Signal(64), # not connected
204 i_int_level_i
= self
.interrupt
,
209 self
.cpu_params
.update(dict(
211 o_TAP_bus__tdo
= self
.jtag_tdo
,
212 i_TAP_bus__tdi
= self
.jtag_tdi
,
213 i_TAP_bus__tms
= self
.jtag_tms
,
214 i_TAP_bus__tck
= self
.jtag_tck
,
217 self
.cpu_params
.update(dict(
219 i_dmi_addr_i
= self
.dmi_addr
,
220 i_dmi_din
= self
.dmi_din
,
221 o_dmi_dout
= self
.dmi_dout
,
222 i_dmi_req_i
= self
.dmi_req
,
223 i_dmi_we_i
= self
.dmi_wr
,
224 o_dmi_ack_o
= self
.dmi_ack
,
227 # add clock select, pll output
228 if variant
== "ls180":
229 self
.pll_48_o
= Signal()
230 self
.clk_sel
= Signal(3)
231 self
.cpu_params
['i_clk_sel_i'] = self
.clk_sel
232 self
.cpu_params
['o_pll_48_o'] = self
.pll_48_o
234 # add wishbone buses to cpu params
235 self
.cpu_params
.update(make_wb_bus("ibus", ibus
))
236 self
.cpu_params
.update(make_wb_bus("dbus", dbus
))
237 self
.cpu_params
.update(make_wb_slave("ics_wb", ics
))
238 self
.cpu_params
.update(make_wb_slave("icp_wb", icp
))
239 if variant
!= "ls180":
240 self
.cpu_params
.update(make_wb_slave("gpio_wb", gpio
))
242 self
.cpu_params
.update(make_wb_bus("jtag_wb", jtag_wb
, simple
=True))
244 if variant
== 'ls180':
245 # urr yuk. have to expose iopads / pins from core to litex
246 # then back again. cut _some_ of that out by connecting
247 self
.padresources
= io()
248 self
.pad_cm
= ConstraintManager(self
.padresources
, [])
252 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
254 for periph
in subset
:
257 if periph
[-1].isdigit():
258 periph
, num
= periph
[:-1], int(periph
[-1])
259 print ("periph request", periph
, num
)
262 periph
, num
= 'spimaster', None
264 periph
, num
= 'spisdcard', None
265 elif periph
== 'sdr':
267 elif periph
== 'mtwi':
270 periph
, num
= 'sdcard', None
271 litexmap
[origperiph
] = (periph
, num
)
272 self
.cpupads
[origperiph
] = platform
.request(periph
, num
)
273 iopads
[origperiph
] = self
.pad_cm
.request(periph
, num
)
274 if periph
== 'sdram':
275 # special-case sdram clock
276 ck
= platform
.request("sdram_clock")
277 self
.cpupads
['sdram_clock'] = ck
278 ck
= self
.pad_cm
.request("sdram_clock")
279 iopads
['sdram_clock'] = ck
281 pinset
= get_pinspecs(subset
=subset
)
284 make_jtag_ioconn(self
.cpu_params
, pin
, self
.cpupads
, iopads
)
286 # add verilog sources
287 self
.add_sources(platform
)
289 def set_reset_address(self
, reset_address
):
290 assert not hasattr(self
, "reset_address")
291 self
.reset_address
= reset_address
292 assert reset_address
== 0x00000000
295 def add_sources(platform
):
296 cdir
= os
.path
.dirname(__file__
)
297 platform
.add_source(os
.path
.join(cdir
, "libresoc.v"))
299 def do_finalize(self
):
300 self
.specials
+= Instance("test_issuer", **self
.cpu_params
)