src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8 CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
   9
  10
  11 def make_wb_bus(prefix, obj, simple=False):
  12     res = {}
  13     outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  14     if not simple:
  15         outpins += ['cti', 'bte']
  16     for o in outpins:
  17         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  18     for i in ['ack', 'err', 'dat_r']:
  19         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  20     return res
  21
  22 def make_wb_slave(prefix, obj):
  23     res = {}
  24     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  25         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  26     for o in ['ack', 'err', 'dat_r']:
  27         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  28     return res
  29
  30
  31 class LibreSoC(CPU):
  32     name                 = "libre_soc"
  33     human_name           = "Libre-SoC"
  34     variants             = CPU_VARIANTS
  35     endianness           = "little"
  36     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  37     linker_output_format = "elf64-powerpcle"
  38     nop                  = "nop"
  39     io_regions           = {0xc0000000: 0x10000000} # origin, length
  40
  41     @property
  42     def mem_map(self):
  43         return {"csr": 0xc0000000}
  44
  45     @property
  46     def gcc_flags(self):
  47         flags  = "-m64 "
  48         flags += "-mabi=elfv2 "
  49         flags += "-msoft-float "
  50         flags += "-mno-string "
  51         flags += "-mno-multiple "
  52         flags += "-mno-vsx "
  53         flags += "-mno-altivec "
  54         flags += "-mlittle-endian "
  55         flags += "-mstrict-align "
  56         flags += "-fno-stack-protector "
  57         flags += "-mcmodel=small "
  58         flags += "-D__microwatt__ "
  59         return flags
  60
  61     def __init__(self, platform, variant="standard"):
  62         self.platform     = platform
  63         self.variant      = variant
  64         self.reset        = Signal()
  65         self.interrupt    = Signal(16)
  66
  67         if variant == "standard32":
  68             self.data_width           = 32
  69             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
  70         else:
  71             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
  72             self.data_width           = 64
  73         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
  74
  75         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
  76         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
  77
  78         jtag_en = ('jtag' in variant) or variant == 'ls180'
  79
  80         if variant != "ls180":
  81             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
  82         if jtag_en:
  83             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
  84
  85         self.periph_buses = [ibus, dbus]
  86         self.memory_buses = []
  87
  88         if jtag_en:
  89             self.periph_buses.append(jtag_wb)
  90             self.jtag_tck = Signal(1)
  91             self.jtag_tms = Signal(1)
  92             self.jtag_tdi = Signal(1)
  93             self.jtag_tdo = Signal(1)
  94         else:
  95             self.dmi_addr = Signal(4)
  96             self.dmi_din = Signal(64)
  97             self.dmi_dout = Signal(64)
  98             self.dmi_wr = Signal(1)
  99             self.dmi_ack = Signal(1)
 100             self.dmi_req = Signal(1)
 101
 102         # # #
 103
 104         self.cpu_params = dict(
 105             # Clock / Reset
 106             i_clk              = ClockSignal(),
 107             i_rst              = ResetSignal() | self.reset,
 108
 109             # Monitoring / Debugging
 110             i_pc_i             = 0,
 111             i_pc_i_ok          = 0,
 112             i_core_bigendian_i = 0, # Signal(),
 113             o_busy_o           = Signal(),   # not connected
 114             o_memerr_o         = Signal(),   # not connected
 115             o_pc_o             = Signal(64), # not connected
 116
 117             # interrupts
 118             i_int_level_i      = self.interrupt,
 119
 120         )
 121
 122         if jtag_en:
 123             self.cpu_params.update(dict(
 124                 # JTAG Debug bus
 125                 o_TAP_bus__tdo = self.jtag_tdo,
 126                 i_TAP_bus__tdi = self.jtag_tdi,
 127                 i_TAP_bus__tms = self.jtag_tms,
 128                 i_TAP_bus__tck = self.jtag_tck,
 129             ))
 130         else:
 131             self.cpu_params.update(dict(
 132                 # DMI Debug bus
 133                 i_dmi_addr_i          = self.dmi_addr,
 134                 i_dmi_din             = self.dmi_din,
 135                 o_dmi_dout            = self.dmi_dout,
 136                 i_dmi_req_i           = self.dmi_req,
 137                 i_dmi_we_i            = self.dmi_wr,
 138                 o_dmi_ack_o           = self.dmi_ack,
 139             ))
 140
 141         # add wishbone buses to cpu params
 142         self.cpu_params.update(make_wb_bus("ibus", ibus))
 143         self.cpu_params.update(make_wb_bus("dbus", dbus))
 144         self.cpu_params.update(make_wb_slave("ics_wb", ics))
 145         self.cpu_params.update(make_wb_slave("icp_wb", icp))
 146         if variant != "ls180":
 147             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
 148         if jtag_en:
 149             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 150
 151         # add verilog sources
 152         self.add_sources(platform)
 153
 154     def set_reset_address(self, reset_address):
 155         assert not hasattr(self, "reset_address")
 156         self.reset_address = reset_address
 157         assert reset_address == 0x00000000
 158
 159     @staticmethod
 160     def add_sources(platform):
 161         cdir = os.path.dirname(__file__)
 162         platform.add_source(os.path.join(cdir, "libresoc.v"))
 163
 164     def do_finalize(self):
 165         self.specials += Instance("test_issuer", **self.cpu_params)
 166