src/soc/litex/sim.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2020 Dolu1990 <charles.papon.90@gmail.com>
   5 # License: BSD
   6
   7 import os
   8 import argparse
   9
  10 from litex.build.generic_platform import Pins, Subsignal
  11 from litex.build.sim import SimPlatform
  12 from litex.build.io import CRG
  13 from litex.build.sim.config import SimConfig
  14
  15 from litex.soc.integration.soc import SoCRegion
  16 from litex.soc.integration.soc_core import SoCCore
  17 from litex.soc.integration.common import get_mem_data
  18 from litex.soc.integration.builder import Builder
  19
  20 from litedram.modules import IS42S16160, MT41K128M16
  21 from litedram.phy.model import SDRAMPHYModel
  22 from litedram.core.controller import ControllerSettings
  23
  24 from litex.tools.litex_sim import get_sdram_phy_settings
  25
  26 from soc.litex.core import LibreSOC
  27
  28 # IOs ------------------------------------------------------------------
  29
  30 _io = [
  31     ("sys_clk", 0, Pins(1)),
  32     ("sys_rst", 0, Pins(1)),
  33     ("serial", 0,
  34         Subsignal("source_valid", Pins(1)),
  35         Subsignal("source_ready", Pins(1)),
  36         Subsignal("source_data",  Pins(8)),
  37
  38         Subsignal("sink_valid", Pins(1)),
  39         Subsignal("sink_ready", Pins(1)),
  40         Subsignal("sink_data",  Pins(8)),
  41     ),
  42 ]
  43
  44 # Platform --------------------------------------------------------------
  45
  46 class Platform(SimPlatform):
  47     def __init__(self):
  48         SimPlatform.__init__(self, "SIM", _io)
  49
  50 # SoCSMP ----------------------------------------------------------------
  51
  52 class SoCSMP(SoCCore):
  53     def __init__(self, cpu_variant, init_memories=False, with_sdcard=False):
  54         platform     = Platform()
  55         sys_clk_freq = int(100e6)
  56
  57         sdram_init = []
  58         if init_memories:
  59             sdram_init = get_mem_data({
  60                 "images/fw_jump.bin": "0x00f00000",
  61                 "images/Image":       "0x00000000",
  62                 "images/dtb"  :       "0x00ef0000",
  63                 "images/rootfs.cpio": "0x01000000",
  64                 }, "little")
  65
  66         # SoCCore --------------------------------------------------------
  67         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
  68             cpu_type                 = "microwatt", # XXX use microwatt
  69             cpu_variant              = cpu_variant,
  70             cpu_cls                  = LibreSOC,
  71             bus_data_width           = 32, # XXX TODO 64 bit wishbone data bus
  72             uart_name                = "sim",
  73             integrated_rom_size      = 0x8000,
  74             integrated_main_ram_size = 0x00000000)
  75
  76         self.platform.name = "sim"
  77         self.add_constant("SIM")
  78
  79         # CRG -------------------------------------------------------
  80         self.submodules.crg = CRG(platform.request("sys_clk"))
  81
  82         # SDRAM ----------------------------------------------------------
  83         if False:
  84             phy_settings = get_sdram_phy_settings(
  85                 #memtype    = "DDR3",
  86                 memtype    = "SDR",
  87                 data_width = 16,
  88                 clk_freq   = 100e6)
  89             self.submodules.sdrphy = SDRAMPHYModel(
  90                 #module    = MT41K128M16(100e6, "1:4"),
  91                 module                  = IS42S16160(100e6, "1:4"),
  92                 settings  = phy_settings,
  93                 clk_freq  = 100e6,
  94                 init      = sdram_init)
  95             self.add_sdram("sdram",
  96                 phy                     = self.sdrphy,
  97                 #module                  = MT41K128M16(100e6, "1:4"),
  98                 module                  = IS42S16160(100e6, "1:4"),
  99                 origin                  = self.mem_map["main_ram"],
 100                 #controller_settings     = ControllerSettings(
 101                 #    cmd_buffer_buffered = False,
 102                 #    with_auto_precharge = True
 103                 #)
 104             )
 105         if init_memories:
 106             addr = 0x40f00000
 107             self.add_constant("MEMTEST_BUS_SIZE",  0) # Skip test if memory is
 108             self.add_constant("MEMTEST_ADDR_SIZE", 0) # initialized to avoid
 109             self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content.
 110             self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin
 111         else:
 112             self.add_constant("MEMTEST_BUS_SIZE",  4096//64)
 113             self.add_constant("MEMTEST_ADDR_SIZE", 4096//256)
 114             self.add_constant("MEMTEST_DATA_SIZE", 4096//32)
 115
 116         # SDCard -----------------------------------------------------
 117         if with_sdcard:
 118             self.add_sdcard("sdcard", use_emulator=True)
 119
 120 # Build -----------------------------------------------------------------
 121
 122 def main():
 123     parser = argparse.ArgumentParser(
 124                         description="Linux on LiteX-LibreSOC Simulation")
 125     parser.add_argument("--cpu-variant", default="standard",
 126                         help="Select CPU netlist variant")
 127     parser.add_argument("--sdram-init",  action="store_true",
 128                         help="Init SDRAM with Linux images")
 129     parser.add_argument("--with-sdcard", action="store_true",
 130                         help="Enable SDCard support")
 131     parser.add_argument("--trace",       action="store_true",
 132                         help="Enable VCD tracing")
 133     parser.add_argument("--trace-start", default=0,
 134                         help="Cycle to start VCD tracing")
 135     parser.add_argument("--trace-end",   default=-1,
 136                         help="Cycle to end VCD tracing")
 137     parser.add_argument("--opt-level",   default="O3",
 138                         help="Compilation optimization level")
 139     args = parser.parse_args()
 140
 141     sim_config = SimConfig(default_clk="sys_clk")
 142     sim_config.add_module("serial2console", "serial")
 143
 144     for i in range(2):
 145         to_run = (i != 0) # first build (i=0), then run (i=1)
 146         soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run,
 147                      args.with_sdcard)
 148         builder = Builder(soc,
 149             compile_gateware = to_run,
 150             csr_json         = "build/sim/csr.json")
 151         builder.build(sim_config=sim_config,
 152             run         = to_run,
 153             opt_level   = args.opt_level,
 154             trace       = args.trace,
 155             trace_start = int(args.trace_start),
 156             trace_end   = int(args.trace_end),
 157             trace_fst   = 0)
 158         os.chdir("../")
 159         #if not to_run:
 160         #  os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME
 161         #  os.system("dtc -O dtb -o images/dtb build/sim/dts") # FIXME
 162         #  os.system("cp verilog/*.bin build/sim/gateware/")
 163
 164 if __name__ == "__main__":
 165     main()