1 from nmigen
import Elaboratable
, Signal
, Module
, Mux
, Repl
, Array
2 from .config
import MemoryPipeConfig
3 from .l1_cache_memory
import L1CacheMemory
6 class MemoryPipe(Elaboratable
):
7 def __init__(self
, config
: MemoryPipeConfig
):
9 self
.l1_cache_memory
= L1CacheMemory(config
)
10 # FIXME(programmerjake): add MemoryQueue as submodule and wire everything up
12 def elaborate(self
, platform
):
14 m
.submodules
.l1_cache_memory
= self
.l1_cache_memory