src/soc/memory_pipe_experiment/memory_pipe.py

   1 from nmigen import Elaboratable, Signal, Module, Mux, Repl, Array
   2 from .config import MemoryPipeConfig
   3 from .l1_cache_memory import L1CacheMemory
   4
   5
   6 class MemoryPipe(Elaboratable):
   7     def __init__(self, config: MemoryPipeConfig):
   8         self.config = config
   9         self.l1_cache_memory = L1CacheMemory(config)
  10         # FIXME(programmerjake): add MemoryQueue as submodule and wire everything up
  11
  12     def elaborate(self, platform):
  13         m = Module()
  14         m.submodules.l1_cache_memory = self.l1_cache_memory
  15         return m