src/soc/memory_pipe_experiment/memory_queue_entry.py

   1 from nmigen import Elaboratable, Module, Signal
   2 from .config import MemoryPipeConfig
   3 from .memory_op import MemoryOpData
   4
   5
   6 class MemoryQueueEntryComb(Elaboratable):
   7     """ Combinatorial state calculation for a memory queue entry, without shifting. """
   8
   9     def __init__(self, config: MemoryPipeConfig):
  10         self.config = config
  11         self.op = MemoryOpData(config)
  12         self.op_out = MemoryOpData(config)
  13
  14     def elaborate(self, platform):
  15         m = Module()
  16
  17         kind = self.op.kind
  18         is_cachable = self.op.is_cachable
  19         is_acquire_operation = self.op.is_acquire_operation
  20         is_release_operation = self.op.is_release_operation
  21         is_speculative = self.op.is_speculative
  22         physical_address = self.op.physical_address
  23         byte_mask = self.op.byte_mask
  24         fu_op_id = self.op.fu_op_id
  25
  26         # FIXME(programmerjake): wire up actual operations
  27
  28         m.d.comb += self.op_out.kind.eq(kind)
  29         m.d.comb += self.op_out.is_cachable.eq(is_cachable)
  30         m.d.comb += self.op_out.is_acquire_operation.eq(is_acquire_operation)
  31         m.d.comb += self.op_out.is_release_operation.eq(is_release_operation)
  32         m.d.comb += self.op_out.is_speculative.eq(is_speculative)
  33         m.d.comb += self.op_out.physical_address.eq(physical_address)
  34         m.d.comb += self.op_out.byte_mask.eq(byte_mask)
  35         m.d.comb += self.op_out.fu_op_id.eq(fu_op_id)
  36         return m
  37
  38
  39 class MemoryQueueEntry(Elaboratable):
  40     def __init__(self, config: MemoryPipeConfig):
  41         self.config = config
  42         self.op = MemoryOpData(config)
  43         self.next_op = MemoryOpData(config)
  44
  45         """ `next_op` of corresponding memory queue entry in the next chunk towards the back of the queue. """
  46         self.next_back_chunks_next_op = MemoryOpData(config)
  47         self.do_shift = Signal()
  48         self.entry_comb = MemoryQueueEntryComb(config)
  49
  50     def elaborate(self, platform):
  51         m = Module()
  52         m.submodules.entry_comb = self.entry_comb
  53         m.d.comb += self.entry_comb.op.eq(self.op)
  54         m.d.comb += self.next_op.eq(self.entry_comb.op_out)
  55         with m.If(self.do_shift):
  56             m.d.sync += self.op.eq(self.next_back_chunks_next_op)
  57         with m.Else():
  58             m.d.sync += self.op.eq(self.next_op)
  59         return m