src/soc/regfile/regfiles.py

   1 # POWER9 Register Files
   2 """POWER9 regfiles
   3
   4 Defines the following register files:
   5
   6     * INT regfile   - 32x 64-bit
   7     * SPR regfile   - 110x 64-bit
   8     * CR regfile    - CR0-7
   9     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
  10     * FAST regfile  - CTR, LR, TAR, SRR1, SRR2
  11     * STATE regfile  - PC, MSR, (SimpleV VL later)
  12
  13 Note: this should NOT have name conventions hard-coded (dedicated ports per
  14 regname).  However it is convenient for now.
  15
  16 Links:
  17
  18 * https://bugs.libre-soc.org/show_bug.cgi?id=345
  19 * https://bugs.libre-soc.org/show_bug.cgi?id=351
  20 * https://libre-soc.org/3d_gpu/architecture/regfile/
  21 * https://libre-soc.org/openpower/isatables/sprs.csv
  22 """
  23
  24 # TODO
  25
  26 from soc.regfile.regfile import RegFile, RegFileArray, RegFileMem
  27 from soc.regfile.virtual_port import VirtualRegPort
  28 from soc.decoder.power_enums import SPR
  29
  30
  31 # "State" Regfile
  32 class StateRegs(RegFileArray):
  33     """StateRegs
  34
  35     State regfile  - PC, MSR and later SimpleV VL
  36
  37     * QTY 2of 64-bit registers
  38     * 3R2W
  39     * Array-based unary-indexed (not binary-indexed)
  40     * write-through capability (read on same cycle as write)
  41
  42     Note: d_wr1 d_rd1 are for use by the decoder, to get at the PC.
  43     will probably have to also add one so it can get at the MSR as well.
  44     (d_rd2)
  45     """
  46     PC = 0
  47     MSR = 1
  48     def __init__(self):
  49         super().__init__(64, 2)
  50         self.w_ports = {'nia': self.write_port("nia"),
  51                         'msr': self.write_port("msr"),
  52                         'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
  53         self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
  54                         'msr': self.read_port("msr"), # reading MSR (issuer)
  55                         }
  56
  57
  58 # Integer Regfile
  59 class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
  60     """IntRegs
  61
  62     * QTY 32of 64-bit registers
  63     * 3R2W
  64     * Array-based unary-indexed (not binary-indexed)
  65     * write-through capability (read on same cycle as write)
  66     """
  67     def __init__(self):
  68         super().__init__(64, 32)
  69         self.w_ports = {'o': self.write_port("dest1"),
  70                         #'o1': self.write_port("dest2") # for now (LD/ST update)
  71                         }
  72         self.r_ports = {'rabc': self.read_port("src1"),
  73                         #'rbc': self.read_port("src3"),
  74                         'dmi': self.read_port("dmi")} # needed for Debug (DMI)
  75
  76
  77 # Fast SPRs Regfile
  78 class FastRegs(RegFileMem): #RegFileArray):
  79     """FastRegs
  80
  81     FAST regfile  - CTR, LR, TAR, SRR1, SRR2
  82
  83     * QTY 5of 64-bit registers
  84     * 2R1W
  85     * Array-based unary-indexed (not binary-indexed)
  86     * write-through capability (read on same cycle as write)
  87     """
  88     CTR = 0
  89     LR = 1
  90     TAR = 2
  91     SRR0 = 3
  92     SRR1 = 4
  93     def __init__(self):
  94         super().__init__(64, 5)
  95         self.w_ports = {'fast1': self.write_port("dest3"),
  96                        }
  97         self.r_ports = {'fast1': self.read_port("src1"),
  98                         }
  99
 100
 101 # CR Regfile
 102 class CRRegs(VirtualRegPort):
 103     """Condition Code Registers (CR0-7)
 104
 105     * QTY 8of 8-bit registers
 106     * 3R1W 4-bit-wide with additional 1R1W for the "full" 32-bit width
 107     * Array-based unary-indexed (not binary-indexed)
 108     * write-through capability (read on same cycle as write)
 109     """
 110     def __init__(self):
 111         super().__init__(32, 8)
 112         self.w_ports = {'full_cr': self.full_wr, # 32-bit (masked, 8-en lines)
 113                         'cr_a': self.write_port("dest1"), # 4-bit, unary-indexed
 114                         'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed
 115         self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
 116                         'cr_a': self.read_port("src1"),
 117                         'cr_b': self.read_port("src2"),
 118                         'cr_c': self.read_port("src3")}
 119
 120
 121 # XER Regfile
 122 class XERRegs(VirtualRegPort):
 123     """XER Registers (SO, CA/CA32, OV/OV32)
 124
 125     * QTY 3of 2-bit registers
 126     * 3R3W 2-bit-wide with additional 1R1W for the "full" 6-bit width
 127     * Array-based unary-indexed (not binary-indexed)
 128     * write-through capability (read on same cycle as write)
 129     """
 130     SO=0 # this is actually 2-bit but we ignore 1 bit of it
 131     CA=1 # CA and CA32
 132     OV=2 # OV and OV32
 133     def __init__(self):
 134         super().__init__(6, 3)
 135         self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
 136                         'xer_so': self.write_port("dest1"),
 137                         'xer_ca': self.write_port("dest2"),
 138                         'xer_ov': self.write_port("dest3")}
 139         self.r_ports = {'full_xer': self.full_rd, # 6-bit (masked, 3-en lines)
 140                         'xer_so': self.read_port("src1"),
 141                         'xer_ca': self.read_port("src2"),
 142                         'xer_ov': self.read_port("src3")}
 143
 144
 145 # SPR Regfile
 146 class SPRRegs(RegFileMem):
 147     """SPRRegs
 148
 149     * QTY len(SPRs) 64-bit registers
 150     * 1R1W
 151     * binary-indexed but REQUIRES MAPPING
 152     * write-through capability (read on same cycle as write)
 153     """
 154     def __init__(self):
 155         n_sprs = len(SPR)
 156         super().__init__(width=64, depth=n_sprs)
 157         self.w_ports = {'spr1': self.write_port("spr1")}
 158         self.r_ports = {'spr1': self.read_port("spr1")}
 159
 160
 161 # class containing all regfiles: int, cr, xer, fast, spr
 162 class RegFiles:
 163     def __init__(self):
 164         self.rf = {}
 165         for (name, kls) in [('int', IntRegs),
 166                             ('cr', CRRegs),
 167                             ('xer', XERRegs),
 168                             ('fast', FastRegs),
 169                             ('state', StateRegs),
 170                             ('spr', SPRRegs),]:
 171             rf = self.rf[name] = kls()
 172             setattr(self, name, rf)
 173
 174     def elaborate_into(self, m, platform):
 175         for (name, rf) in self.rf.items():
 176             setattr(m.submodules, name, rf)
 177         return m
 178