move SVP64 Extra reg decoding into main PowerDecoder module
[soc.git] / src / soc / scoreboard / fu_picker_vec.py
1 from nmigen import Elaboratable, Module, Signal, Cat
2
3
4 class FU_Pick_Vec(Elaboratable):
5 """ these are allocated per-FU (horizontally),
6 and are of length fu_row_n
7 """
8 def __init__(self, fu_row_n):
9 self.fu_row_n = fu_row_n
10 self.rd_pend_i = Signal(fu_row_n, reset_less=True)
11 self.wr_pend_i = Signal(fu_row_n, reset_less=True)
12
13 self.readable_o = Signal(reset_less=True)
14 self.writable_o = Signal(reset_less=True)
15
16 def elaborate(self, platform):
17 m = Module()
18
19 # Readable if there are no writes pending
20 m.d.comb += self.readable_o.eq(~self.wr_pend_i.bool())
21
22 # Writable if there are no reads pending
23 m.d.comb += self.writable_o.eq(~self.rd_pend_i.bool())
24
25 return m
26