src/soc/scoreboard/group_picker.py

   1 """ Group Picker: to select an instruction that is permitted to read (or write)
   2     based on the Function Unit expressing a *desire* to read (or write).
   3
   4     The job of the Group Picker is extremely simple yet extremely important.
   5     It sits in front of a register file port (read or write) and stops it from
   6     being corrupted.  It's a "port contention selector", basically.
   7
   8     The way it works is:
   9
  10     * Function Units need to read from (or write to) the register file,
  11       in order to get (or store) their operands, so they each have a signal,
  12       readable (or writable), which "expresses" this need.  This is an
  13       *unary* encoding.
  14
  15     * The Function Units also have a signal which indicates that they
  16       are requesting "release" of the register file port (this because
  17       in the scoreboard, readable/writable can be permanently HI even
  18       if the FU is idle, whereas the "release" signal is very specifically
  19       only HI if the read (or write) latch is still active)
  20
  21     * The Group Picker takes this unary encoding of the desire to read
  22       (or write) and, on a priority basis, activates one *and only* one
  23       of those signals, again as an unary output.
  24
  25     * Due to the way that the Computation Unit works, that signal (Go_Read
  26       or Go_Write) will fire for one (and only one) cycle, and can be used
  27       to enable the register file port read (or write) lines.  The Go_Read/Wr
  28       signal basically loops back to the Computation Unit and resets the
  29       "desire-to-read/write-expressing" latch.
  30
  31     In theory (and in practice!) the following is possible:
  32
  33     * Separate src1 and src2 Group Pickers.  This would allow instructions
  34       with only one operand to read to not block up other instructions,
  35       and it would also allow 3-operand instructions to be interleaved
  36       with 1 and 2 operand instructions.
  37
  38     * *Multiple* Group Pickers (multi-issue).  This would require
  39       a corresponding increase in the number of register file ports,
  40       either 4R2W (or more) or by "striping" the register file into
  41       split banks (a strategy best deployed on Vector Processors)
  42
  43 """
  44
  45 from nmigen.compat.sim import run_simulation
  46 from nmigen.cli import verilog, rtlil
  47 from nmigen import Module, Signal, Elaboratable
  48
  49 from nmutil.picker import PriorityPicker
  50
  51
  52 class GroupPicker(Elaboratable):
  53     """ implements 10.5 mitch alsup group picker, p27
  54     """
  55     def __init__(self, wid):
  56         self.gp_wid = wid
  57         # inputs
  58         self.readable_i = Signal(wid, reset_less=True) # readable in (top)
  59         self.writable_i = Signal(wid, reset_less=True) # writable in (top)
  60         self.rd_rel_i = Signal(wid, reset_less=True)   # go read in (top)
  61         self.req_rel_i = Signal(wid, reset_less=True) # release request in (top)
  62
  63         # outputs
  64         self.go_rd_o = Signal(wid, reset_less=True)  # go read (bottom)
  65         self.go_wr_o = Signal(wid, reset_less=True)  # go write (bottom)
  66
  67     def elaborate(self, platform):
  68         m = Module()
  69
  70         m.submodules.rpick = rpick = PriorityPicker(self.gp_wid)
  71         m.submodules.wpick = wpick = PriorityPicker(self.gp_wid)
  72
  73         # combine release (output ready signal) with writeable
  74         m.d.comb += wpick.i.eq(self.writable_i & self.req_rel_i)
  75         m.d.comb += self.go_wr_o.eq(wpick.o)
  76
  77         m.d.comb += rpick.i.eq(self.readable_i & self.rd_rel_i)
  78         m.d.comb += self.go_rd_o.eq(rpick.o)
  79
  80         return m
  81
  82     def __iter__(self):
  83         yield self.readable_i
  84         yield self.writable_i
  85         yield self.req_rel_i
  86         yield self.go_rd_o
  87         yield self.go_wr_o
  88
  89     def ports(self):
  90         return list(self)
  91
  92
  93 def grp_pick_sim(dut):
  94     yield dut.dest_i.eq(1)
  95     yield dut.issue_i.eq(1)
  96     yield
  97     yield dut.issue_i.eq(0)
  98     yield
  99     yield dut.src1_i.eq(1)
 100     yield dut.issue_i.eq(1)
 101     yield
 102     yield
 103     yield
 104     yield dut.issue_i.eq(0)
 105     yield
 106     yield dut.rd_rel_i.eq(1)
 107     yield
 108     yield dut.rd_rel_i.eq(0)
 109     yield
 110     yield dut.go_wr_i.eq(1)
 111     yield
 112     yield dut.go_wr_i.eq(0)
 113     yield
 114
 115 def test_grp_pick():
 116     dut = GroupPicker(4)
 117     vl = rtlil.convert(dut, ports=dut.ports())
 118     with open("test_grp_pick.il", "w") as f:
 119         f.write(vl)
 120
 121     run_simulation(dut, grp_pick_sim(dut), vcd_name='test_grp_pick.vcd')
 122
 123 if __name__ == '__main__':
 124     test_grp_pick()