src/soc/scoremulti/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl
   4
   5 from soc.scoremulti.dependence_cell import DependencyRow
   6 from soc.scoremulti.fu_wr_pending import FU_RW_Pend
   7 from soc.scoremulti.reg_sel import Reg_Rsv
   8 from soc.scoreboard.global_pending import GlobalPending
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col, n_src, n_dest, cancel=None):
  32         self.n_src = n_src
  33         self.n_dest = n_dest
  34         self.n_fu_row = nf = n_fu_row      # Y (FUs)   ^v
  35         self.n_reg_col = n_reg = n_reg_col   # X (Regs)  <>
  36
  37         # arrays
  38         src = []
  39         rsel = []
  40         rd = []
  41         for i in range(n_src):
  42             j = i + 1 # name numbering to match src1/src2
  43             src.append(Signal(n_reg, name="src%d" % j, reset_less=True))
  44             rsel.append(Signal(n_reg, name="src%d_rsel_o" % j, reset_less=True))
  45             rd.append(Signal(nf, name="gord%d_i" % j, reset_less=True))
  46         dst = []
  47         dsel = []
  48         wr = []
  49         for i in range(n_src):
  50             j = i + 1 # name numbering to match src1/src2
  51             dst.append(Signal(n_reg, name="dst%d" % j, reset_less=True))
  52             dsel.append(Signal(n_reg, name="dst%d_rsel_o" % j, reset_less=True))
  53             wr.append(Signal(nf, name="gowr%d_i" % j, reset_less=True))
  54         wpnd = []
  55         pend = []
  56         for i in range(nf):
  57             j = i + 1 # name numbering to match src1/src2
  58             pend.append(Signal(nf, name="rd_src%d_pend_o" % j, reset_less=True))
  59             wpnd.append(Signal(nf, name="wr_dst%d_pend_o" % j, reset_less=True))
  60
  61         self.dest_i = Array(dst)     # Dest in (top)
  62         self.src_i = Array(src)      # oper in (top)
  63
  64         # cancellation array (from Address Matching), ties in with go_die_i
  65         self.cancel = cancel
  66
  67         # Register "Global" vectors for determining RaW and WaR hazards
  68         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
  69         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
  70         self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
  71         self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
  72
  73         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
  74         self.go_wr_i = Array(wr)  # Go Write in (left)
  75         self.go_rd_i = Array(rd)  # Go Read in (left)
  76         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  77
  78         # for Register File Select Lines (horizontal), per-reg
  79         self.dest_rsel_o = Array(dsel) # dest reg (bot)
  80         self.src_rsel_o = Array(rsel)  # src reg (bot)
  81
  82         # for Function Unit "forward progress" (vertical), per-FU
  83
  84         # global "merged" (all regs) src/dest pending vectors
  85         self.wr_dst_pend_o = Array(wpnd) # dest pending
  86         self.rd_src_pend_o = Array(pend) # src1 pending
  87
  88         # per-port src/dest pending vectors
  89         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  90         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  91
  92     def elaborate(self, platform):
  93         m = Module()
  94         return self._elaborate(m, platform)
  95
  96     def _elaborate(self, m, platform):
  97
  98         # ---
  99         # matrix of dependency cells
 100         # ---
 101         cancel_mode = self.cancel is not None
 102         dm = Array(DependencyRow(self.n_reg_col, self.n_src,
 103                                  self.n_dest, cancel_mode) \
 104                     for r in range(self.n_fu_row))
 105         for fu in range(self.n_fu_row):
 106             setattr(m.submodules, "dr_fu%d" % fu, dm[fu])
 107
 108         # ---
 109         # array of Function Unit Pending vectors
 110         # ---
 111         fupend = Array(FU_RW_Pend(self.n_reg_col, self.n_src, self.n_dest) \
 112                         for f in range(self.n_fu_row))
 113         for fu in range(self.n_fu_row):
 114             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
 115
 116         # ---
 117         # array of Register Reservation vectors
 118         # ---
 119         regrsv = Array(Reg_Rsv(self.n_fu_row, self.n_src, self.n_dest) \
 120                         for r in range(self.n_reg_col))
 121         for rn in range(self.n_reg_col):
 122             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
 123
 124         # ---
 125         # connect Function Unit vector
 126         # ---
 127         wr_pend = []
 128         rd_pend = []
 129         for fu in range(self.n_fu_row):
 130             fup = fupend[fu]
 131             # accumulate FU Vector outputs
 132             wr_pend.append(fup.reg_wr_pend_o)
 133             rd_pend.append(fup.reg_rd_pend_o)
 134
 135         # ... and output them from this module (vertical, width=FUs)
 136         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 137         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 138
 139         # same for dest
 140         for i in range(self.n_dest):
 141             wr_dst_pend = []
 142             for fu in range(self.n_fu_row):
 143                 dc = dm[fu]
 144                 fup = fupend[fu]
 145                 dst_fwd_o = []
 146                 for rn in range(self.n_reg_col):
 147                     # accumulate cell fwd outputs for dest/src1/src2
 148                     dst_fwd_o.append(dc.dest_fwd_o[i][rn])
 149                 # connect cell fwd outputs to FU Vector in [Cat is gooood]
 150                 m.d.comb += [fup.dest_fwd_i[i].eq(Cat(*dst_fwd_o)),
 151                             ]
 152                 # accumulate FU Vector outputs
 153                 wr_dst_pend.append(fup.reg_wr_dst_pend_o[i])
 154             # ... and output them from this module (vertical, width=FUs)
 155             m.d.comb += self.wr_dst_pend_o[i].eq(Cat(*wr_dst_pend))
 156
 157         # same for src
 158         for i in range(self.n_src):
 159             rd_src_pend = []
 160             for fu in range(self.n_fu_row):
 161                 dc = dm[fu]
 162                 fup = fupend[fu]
 163                 src_fwd_o = []
 164                 for rn in range(self.n_reg_col):
 165                     # accumulate cell fwd outputs for dest/src1/src2
 166                     src_fwd_o.append(dc.src_fwd_o[i][rn])
 167                 # connect cell fwd outputs to FU Vector in [Cat is gooood]
 168                 m.d.comb += [fup.src_fwd_i[i].eq(Cat(*src_fwd_o)),
 169                             ]
 170                 # accumulate FU Vector outputs
 171                 rd_src_pend.append(fup.reg_rd_src_pend_o[i])
 172             # ... and output them from this module (vertical, width=FUs)
 173             m.d.comb += self.rd_src_pend_o[i].eq(Cat(*rd_src_pend))
 174
 175         # ---
 176         # connect Reg Selection vector
 177         # ---
 178         for i in range(self.n_dest):
 179             dest_rsel = []
 180             for rn in range(self.n_reg_col):
 181                 rsv = regrsv[rn]
 182                 dest_rsel_o = []
 183                 for fu in range(self.n_fu_row):
 184                     dc = dm[fu]
 185                     # accumulate cell reg-select outputs dest/src1/src2
 186                     dest_rsel_o.append(dc.dest_rsel_o[i][rn])
 187                 # connect cell reg-select outputs to Reg Vector In
 188                 m.d.comb += rsv.dest_rsel_i[i].eq(Cat(*dest_rsel_o)),
 189
 190                 # accumulate Reg-Sel Vector outputs
 191                 dest_rsel.append(rsv.dest_rsel_o[i])
 192
 193         # ... and output them from this module (horizontal, width=REGs)
 194         m.d.comb += self.dest_rsel_o[i].eq(Cat(*dest_rsel))
 195
 196         # same for src
 197         for i in range(self.n_src):
 198             src_rsel = []
 199             for rn in range(self.n_reg_col):
 200                 rsv = regrsv[rn]
 201                 src_rsel_o = []
 202                 for fu in range(self.n_fu_row):
 203                     dc = dm[fu]
 204                     # accumulate cell reg-select outputs dest/src1/src2
 205                     src_rsel_o.append(dc.src_rsel_o[i][rn])
 206                 # connect cell reg-select outputs to Reg Vector In
 207                 m.d.comb += rsv.src_rsel_i[i].eq(Cat(*src_rsel_o)),
 208                 # accumulate Reg-Sel Vector outputs
 209                 src_rsel.append(rsv.src_rsel_o[i])
 210
 211             # ... and output them from this module (horizontal, width=REGs)
 212             m.d.comb += self.src_rsel_o[i].eq(Cat(*src_rsel))
 213
 214         # ---
 215         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 216         # ---
 217         for fu in range(self.n_fu_row):
 218             dc = dm[fu]
 219             # wire up inputs from module to row cell inputs (Cat is gooood)
 220             m.d.comb += [dc.rd_pend_i.eq(self.rd_pend_i),
 221                          dc.wr_pend_i.eq(self.wr_pend_i),
 222                         ]
 223         # same for dest
 224         for i in range(self.n_dest):
 225             for fu in range(self.n_fu_row):
 226                 dc = dm[fu]
 227                 # wire up inputs from module to row cell inputs (Cat is gooood)
 228                 m.d.comb += dc.dest_i[i].eq(self.dest_i[i])
 229
 230         # same for src
 231         for i in range(self.n_src):
 232             for fu in range(self.n_fu_row):
 233                 dc = dm[fu]
 234                 # wire up inputs from module to row cell inputs (Cat is gooood)
 235                 m.d.comb += dc.src_i[i].eq(self.src_i[i])
 236
 237         # accumulate rsel bits into read/write pending vectors.
 238         rd_pend_v = []
 239         wr_pend_v = []
 240         for fu in range(self.n_fu_row):
 241             dc = dm[fu]
 242             rd_pend_v.append(dc.v_rd_rsel_o)
 243             wr_pend_v.append(dc.v_wr_rsel_o)
 244         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
 245         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
 246         m.submodules.rd_v = rd_v
 247         m.submodules.wr_v = wr_v
 248
 249         m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
 250         m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 251
 252         # ---
 253         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
 254         # ---
 255         issue_i = []
 256         for fu in range(self.n_fu_row):
 257             dc = dm[fu]
 258             issue_i.append(dc.issue_i)
 259         # wire up inputs from module to row cell inputs (Cat is gooood)
 260         m.d.comb += Cat(*issue_i).eq(self.issue_i)
 261
 262         for i in range(self.n_src):
 263             go_rd_i = []
 264             for fu in range(self.n_fu_row):
 265                 dc = dm[fu]
 266                 # accumulate cell fwd outputs for dest/src1/src2
 267                 go_rd_i.append(dc.go_rd_i[i])
 268             # wire up inputs from module to row cell inputs (Cat is gooood)
 269             m.d.comb += Cat(*go_rd_i).eq(self.go_rd_i[i])
 270
 271         for i in range(self.n_dest):
 272             go_wr_i = []
 273             for fu in range(self.n_fu_row):
 274                 dc = dm[fu]
 275                 # accumulate cell fwd outputs for dest/src1/src2
 276                 go_wr_i.append(dc.go_wr_i[i])
 277             # wire up inputs from module to row cell inputs (Cat is gooood)
 278             m.d.comb += Cat(*go_wr_i).eq(self.go_wr_i[i])
 279
 280         # ---
 281         # connect Dep go_die_i
 282         # ---
 283         if cancel_mode:
 284             for fu in range(self.n_fu_row):
 285                 dc = dm[fu]
 286                 go_die = Repl(self.go_die_i[fu], self.n_fu_row)
 287                 go_die = go_die | self.cancel[fu]
 288                 m.d.comb += dc.go_die_i.eq(go_die)
 289         else:
 290             go_die_i = []
 291             for fu in range(self.n_fu_row):
 292                 dc = dm[fu]
 293                 # accumulate cell fwd outputs for dest/src1/src2
 294                 go_die_i.append(dc.go_die_i)
 295             # wire up inputs from module to row cell inputs (Cat is gooood)
 296             m.d.comb += Cat(*go_die_i).eq(self.go_die_i)
 297         return m
 298
 299     def __iter__(self):
 300         yield from self.dest_i
 301         yield from self.src_i
 302         yield self.issue_i
 303         yield from self.go_wr_i
 304         yield from self.go_rd_i
 305         yield self.go_die_i
 306         yield from self.dest_rsel_o
 307         yield from self.src_rsel_o
 308         yield self.wr_pend_o
 309         yield self.rd_pend_o
 310         yield self.wr_pend_i
 311         yield self.rd_pend_i
 312         yield self.v_wr_rsel_o
 313         yield self.v_rd_rsel_o
 314         yield from self.rd_src_pend_o
 315
 316     def ports(self):
 317         return list(self)
 318
 319 def d_matrix_sim(dut):
 320     """ XXX TODO
 321     """
 322     yield dut.dest_i.eq(1)
 323     yield dut.issue_i.eq(1)
 324     yield
 325     yield dut.issue_i.eq(0)
 326     yield
 327     yield dut.src1_i.eq(1)
 328     yield dut.issue_i.eq(1)
 329     yield
 330     yield dut.issue_i.eq(0)
 331     yield
 332     yield dut.go_rd_i.eq(1)
 333     yield
 334     yield dut.go_rd_i.eq(0)
 335     yield
 336     yield dut.go_wr_i.eq(1)
 337     yield
 338     yield dut.go_wr_i.eq(0)
 339     yield
 340
 341 def test_d_matrix():
 342     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4, n_src=2, n_dest=2)
 343     vl = rtlil.convert(dut, ports=dut.ports())
 344     with open("test_fu_reg_matrix.il", "w") as f:
 345         f.write(vl)
 346
 347     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 348
 349 if __name__ == '__main__':
 350     test_d_matrix()