1 from nmigen
import Elaboratable
, Module
, Signal
, Array
4 class Reg_Rsv(Elaboratable
):
5 """ these are allocated per-Register (vertically),
6 and are each of length fu_count
8 def __init__(self
, fu_count
, n_src
, n_dest
):
11 self
.fu_count
= fu_count
12 self
.dest_rsel_i
= Signal(fu_count
, reset_less
=True)
13 self
.dest_rsel_i
= Array(Signal(fu_count
, name
="dst_rsel_i",
15 for i
in range(n_dest
))
16 self
.src_rsel_i
= Array(Signal(fu_count
, name
="src_rsel_i",
18 for i
in range(n_src
))
19 self
.dest_rsel_o
= Signal(n_dest
, reset_less
=True)
20 self
.src_rsel_o
= Signal(n_src
, reset_less
=True)
22 def elaborate(self
, platform
):
24 for i
in range(self
.n_dest
):
25 m
.d
.comb
+= self
.dest_rsel_o
[i
].eq(self
.dest_rsel_i
[i
].bool())
26 for i
in range(self
.n_src
):
27 m
.d
.comb
+= self
.src_rsel_o
[i
].eq(self
.src_rsel_i
[i
].bool())