src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.core_bigendian_i = Signal()
 126         self.busy_o = Signal(reset_less=True)
 127         self.memerr_o = Signal(reset_less=True)
 128
 129         # STATE regfile read /write ports for PC, MSR, SVSTATE
 130         staterf = self.core.regs.rf['state']
 131         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 132         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 133         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 134         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 135         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 136
 137         # DMI interface access
 138         intrf = self.core.regs.rf['int']
 139         crrf = self.core.regs.rf['cr']
 140         xerrf = self.core.regs.rf['xer']
 141         self.int_r = intrf.r_ports['dmi'] # INT read
 142         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 143         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 144
 145         # hack method of keeping an eye on whether branch/trap set the PC
 146         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 147         self.state_nia.wen.name = 'state_nia_wen'
 148
 149     def fetch_fsm(self, m, core, dbg, pc, pc_changed, sv_changed, insn_done,
 150                         core_rst, cur_state,
 151                         fetch_pc_ready_o, fetch_pc_valid_i,
 152                         exec_insn_valid_o, exec_insn_ready_i,
 153                         fetch_insn_o):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163
 164         msr_read = Signal(reset=1)
 165         sv_read = Signal(reset=1)
 166
 167         # address of the next instruction, in the absence of a branch
 168         # depends on the instruction size
 169         nia = Signal(64, reset_less=True)
 170
 171         with m.FSM(name='fetch_fsm'):
 172
 173             # waiting (zzz)
 174             with m.State("IDLE"):
 175                 with m.If(~dbg.core_stop_o & ~core_rst):
 176                     comb += fetch_pc_ready_o.eq(1)
 177                     with m.If(fetch_pc_valid_i):
 178                         # instruction allowed to go: start by reading the PC
 179                         # capture the PC and also drop it into Insn Memory
 180                         # we have joined a pair of combinatorial memory
 181                         # lookups together.  this is Generally Bad.
 182                         comb += self.imem.a_pc_i.eq(pc)
 183                         comb += self.imem.a_valid_i.eq(1)
 184                         comb += self.imem.f_valid_i.eq(1)
 185                         sync += cur_state.pc.eq(pc)
 186
 187                         # initiate read of MSR/SVSTATE. arrives one clock later
 188                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 189                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 190                         sync += msr_read.eq(0)
 191                         sync += sv_read.eq(0)
 192
 193                         m.next = "INSN_READ"  # move to "wait for bus" phase
 194                 with m.Else():
 195                     comb += core.core_stopped_i.eq(1)
 196                     comb += dbg.core_stopped_i.eq(1)
 197
 198             # dummy pause to find out why simulation is not keeping up
 199             with m.State("INSN_READ"):
 200                 # one cycle later, msr/sv read arrives.  valid only once.
 201                 with m.If(~msr_read):
 202                     sync += msr_read.eq(1) # yeah don't read it again
 203                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 204                 with m.If(~sv_read):
 205                     sync += sv_read.eq(1) # yeah don't read it again
 206                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 207                 with m.If(self.imem.f_busy_o): # zzz...
 208                     # busy: stay in wait-read
 209                     comb += self.imem.a_valid_i.eq(1)
 210                     comb += self.imem.f_valid_i.eq(1)
 211                 with m.Else():
 212                     # not busy: instruction fetched
 213                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 214                     # decode the SVP64 prefix, if any
 215                     comb += svp64.raw_opcode_in.eq(insn)
 216                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 217                     # pass the decoded prefix (if any) to PowerDecoder2
 218                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 219                     # calculate the address of the following instruction
 220                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 221                     sync += nia.eq(cur_state.pc + insn_size)
 222                     with m.If(~svp64.is_svp64_mode):
 223                         # with no prefix, store the instruction
 224                         # and hand it directly to the next FSM
 225                         sync += fetch_insn_o.eq(insn)
 226                         m.next = "INSN_READY"
 227                     with m.Else():
 228                         # fetch the rest of the instruction from memory
 229                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 230                         comb += self.imem.a_valid_i.eq(1)
 231                         comb += self.imem.f_valid_i.eq(1)
 232                         m.next = "INSN_READ2"
 233
 234             with m.State("INSN_READ2"):
 235                 with m.If(self.imem.f_busy_o):  # zzz...
 236                     # busy: stay in wait-read
 237                     comb += self.imem.a_valid_i.eq(1)
 238                     comb += self.imem.f_valid_i.eq(1)
 239                 with m.Else():
 240                     # not busy: instruction fetched
 241                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 242                     sync += fetch_insn_o.eq(insn)
 243                     m.next = "INSN_READY"
 244
 245             with m.State("INSN_READY"):
 246                 # hand over the instruction, to be decoded
 247                 comb += exec_insn_valid_o.eq(1)
 248                 with m.If(exec_insn_ready_i):
 249                     m.next = "IDLE"
 250
 251         # code-morph: moving the actual PC-setting out of "execute"
 252         # so that it's easier to move this into an "issue" FSM.
 253
 254         # ok here we are not reading the branch unit.  TODO
 255         # this just blithely overwrites whatever pipeline
 256         # updated the PC
 257         core_busy_o = core.busy_o                 # core is busy
 258         with m.If(insn_done & (~pc_changed) & (~core_busy_o)):
 259             comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 260             comb += self.state_w_pc.data_i.eq(nia)
 261
 262     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 263                         cur_state, fetch_insn_o,
 264                         fetch_pc_ready_o, fetch_pc_valid_i,
 265                         exec_insn_valid_o, exec_insn_ready_i):
 266         """execute FSM
 267
 268         decode / issue / execute FSM.  this interacts with the "fetch" FSM
 269         through fetch_pc_ready/valid (incoming) and exec_insn_ready/valid
 270         (outgoing).  SVP64 RM prefixes have already been set up by the
 271         "fetch" phase, so execute is fairly straightforward.
 272         """
 273
 274         comb = m.d.comb
 275         sync = m.d.sync
 276         pdecode2 = self.pdecode2
 277         svp64 = self.svp64
 278
 279         # temporaries
 280         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 281         core_busy_o = core.busy_o                 # core is busy
 282         core_ivalid_i = core.ivalid_i             # instruction is valid
 283         core_issue_i = core.issue_i               # instruction is issued
 284         insn_type = core.e.do.insn_type           # instruction MicroOp type
 285
 286         with m.FSM():
 287
 288             # go fetch the instruction at the current PC
 289             # at this point, there is no instruction running, that
 290             # could inadvertently update the PC.
 291             with m.State("INSN_FETCH"):
 292                 comb += fetch_pc_valid_i.eq(1)
 293                 with m.If(fetch_pc_ready_o):
 294                     m.next = "INSN_WAIT"
 295
 296             # decode the instruction when it arrives
 297             with m.State("INSN_WAIT"):
 298                 comb += exec_insn_ready_i.eq(1)
 299                 with m.If(exec_insn_valid_o):
 300                     # decode the instruction
 301                     comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 302                     sync += core.e.eq(pdecode2.e)
 303                     sync += core.state.eq(cur_state)
 304                     sync += core.raw_insn_i.eq(dec_opcode_i)
 305                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 306                     # also drop PC and MSR into decode "state"
 307                     m.next = "INSN_START" # move to "start"
 308
 309             # waiting for instruction bus (stays there until not busy)
 310             with m.State("INSN_START"):
 311                 comb += core_ivalid_i.eq(1) # instruction is valid
 312                 comb += core_issue_i.eq(1)  # and issued
 313
 314                 m.next = "INSN_ACTIVE" # move to "wait completion"
 315
 316             # instruction started: must wait till it finishes
 317             with m.State("INSN_ACTIVE"):
 318                 with m.If(insn_type != MicrOp.OP_NOP):
 319                     comb += core_ivalid_i.eq(1) # instruction is valid
 320                 # note changes to PC and SVSTATE
 321                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 322                     sync += sv_changed.eq(1)
 323                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 324                     sync += pc_changed.eq(1)
 325                 with m.If(~core_busy_o): # instruction done!
 326                     comb += insn_done.eq(1)
 327                     sync += core.e.eq(0)
 328                     sync += core.raw_insn_i.eq(0)
 329                     sync += core.bigendian_i.eq(0)
 330                     sync += sv_changed.eq(0)
 331                     sync += pc_changed.eq(0)
 332                     m.next = "INSN_FETCH"  # back to fetch
 333
 334     def elaborate(self, platform):
 335         m = Module()
 336         comb, sync = m.d.comb, m.d.sync
 337
 338         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 339         m.submodules.imem = imem = self.imem
 340         m.submodules.dbg = dbg = self.dbg
 341         if self.jtag_en:
 342             m.submodules.jtag = jtag = self.jtag
 343             # TODO: UART2GDB mux, here, from external pin
 344             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 345             sync += dbg.dmi.connect_to(jtag.dmi)
 346
 347         cur_state = self.cur_state
 348
 349         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 350         if self.sram4x4k:
 351             for i, sram in enumerate(self.sram4k):
 352                 m.submodules["sram4k_%d" % i] = sram
 353                 comb += sram.enable.eq(self.wb_sram_en)
 354
 355         # XICS interrupt handler
 356         if self.xics:
 357             m.submodules.xics_icp = icp = self.xics_icp
 358             m.submodules.xics_ics = ics = self.xics_ics
 359             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 360             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 361
 362         # GPIO test peripheral
 363         if self.gpio:
 364             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 365
 366         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 367         # XXX causes litex ECP5 test to get wrong idea about input and output
 368         # (but works with verilator sim *sigh*)
 369         #if self.gpio and self.xics:
 370         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 371
 372         # instruction decoder
 373         pdecode = create_pdecode()
 374         m.submodules.dec2 = pdecode2 = self.pdecode2
 375         m.submodules.svp64 = svp64 = self.svp64
 376
 377         # convenience
 378         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 379         intrf = self.core.regs.rf['int']
 380
 381         # clock delay power-on reset
 382         cd_por  = ClockDomain(reset_less=True)
 383         cd_sync = ClockDomain()
 384         core_sync = ClockDomain("coresync")
 385         m.domains += cd_por, cd_sync, core_sync
 386
 387         ti_rst = Signal(reset_less=True)
 388         delay = Signal(range(4), reset=3)
 389         with m.If(delay != 0):
 390             m.d.por += delay.eq(delay - 1)
 391         comb += cd_por.clk.eq(ClockSignal())
 392
 393         # power-on reset delay
 394         core_rst = ResetSignal("coresync")
 395         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 396         comb += core_rst.eq(ti_rst)
 397
 398         # busy/halted signals from core
 399         comb += self.busy_o.eq(core.busy_o)
 400         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 401
 402         # temporary hack: says "go" immediately for both address gen and ST
 403         l0 = core.l0
 404         ldst = core.fus.fus['ldst0']
 405         st_go_edge = rising_edge(m, ldst.st.rel_o)
 406         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 407         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 408
 409         # PC and instruction from I-Memory
 410         comb += self.pc_o.eq(cur_state.pc)
 411         pc_changed = Signal() # note write to PC
 412         sv_changed = Signal() # note write to SVSTATE
 413         insn_done = Signal()  # fires just once
 414
 415         # read the PC
 416         pc = Signal(64, reset_less=True)
 417         pc_ok_delay = Signal()
 418         sync += pc_ok_delay.eq(~self.pc_i.ok)
 419         with m.If(self.pc_i.ok):
 420             # incoming override (start from pc_i)
 421             comb += pc.eq(self.pc_i.data)
 422         with m.Else():
 423             # otherwise read StateRegs regfile for PC...
 424             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 425         # ... but on a 1-clock delay
 426         with m.If(pc_ok_delay):
 427             comb += pc.eq(self.state_r_pc.data_o)
 428
 429         # don't write pc every cycle
 430         comb += self.state_w_pc.wen.eq(0)
 431         comb += self.state_w_pc.data_i.eq(0)
 432
 433         # don't read msr or svstate every cycle
 434         comb += self.state_r_sv.ren.eq(0)
 435         comb += self.state_r_msr.ren.eq(0)
 436
 437         # connect up debug signals
 438         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 439         comb += dbg.terminate_i.eq(core.core_terminate_o)
 440         comb += dbg.state.pc.eq(pc)
 441         #comb += dbg.state.pc.eq(cur_state.pc)
 442         comb += dbg.state.msr.eq(cur_state.msr)
 443
 444         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 445         # these are the handshake signals between fetch and decode/execute
 446
 447         # fetch FSM can run as soon as the PC is valid
 448         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 449         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 450
 451         # SVSTATE FSM TODO. actually, an "Issue" FSM that happens to do SVSTATE
 452         fetch_to_sv_ready_i = Signal()
 453         fetch_to_sv_valid_o = Signal()
 454
 455         sv_to_exec_ready_i = Signal()
 456         sv_to_exec_valid_o = Signal()
 457
 458         # when done, deliver the instruction to the next FSM
 459         exec_insn_valid_o = Signal()
 460         exec_insn_ready_i = Signal() # Execute acknowledges SVSTATE
 461
 462         # latches copy of raw fetched instruction
 463         fetch_insn_o = Signal(32, reset_less=True)
 464
 465         # actually use a nmigen FSM for the first time (w00t)
 466         # this FSM is perhaps unusual in that it detects conditions
 467         # then "holds" information, combinatorially, for the core
 468         # (as opposed to using sync - which would be on a clock's delay)
 469         # this includes the actual opcode, valid flags and so on.
 470
 471         self.fetch_fsm(m, core, dbg, pc, pc_changed, sv_changed, insn_done,
 472                        core_rst, cur_state,
 473                        fetch_pc_ready_o, fetch_pc_valid_i,
 474                        exec_insn_valid_o, exec_insn_ready_i,
 475                        fetch_insn_o)
 476
 477         # TODO: an SVSTATE-based for-loop FSM that goes in between
 478         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 479         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 480
 481         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 482                         cur_state, fetch_insn_o,
 483                         fetch_pc_ready_o, fetch_pc_valid_i,
 484                         exec_insn_valid_o, exec_insn_ready_i)
 485
 486         # for updating svstate (things like srcstep etc.)
 487         update_svstate = Signal() # TODO: move this somewhere above
 488         new_svstate = SVSTATERec("new_svstate") # and move this as well
 489         # check if svstate needs updating: if so, write it to State Regfile
 490         with m.If(update_svstate):
 491             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 492             comb += self.state_w_sv.data_i.eq(new_svstate)
 493
 494         # this bit doesn't have to be in the FSM: connect up to read
 495         # regfiles on demand from DMI
 496         with m.If(d_reg.req): # request for regfile access being made
 497             # TODO: error-check this
 498             # XXX should this be combinatorial?  sync better?
 499             if intrf.unary:
 500                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 501             else:
 502                 comb += self.int_r.addr.eq(d_reg.addr)
 503                 comb += self.int_r.ren.eq(1)
 504         d_reg_delay  = Signal()
 505         sync += d_reg_delay.eq(d_reg.req)
 506         with m.If(d_reg_delay):
 507             # data arrives one clock later
 508             comb += d_reg.data.eq(self.int_r.data_o)
 509             comb += d_reg.ack.eq(1)
 510
 511         # sigh same thing for CR debug
 512         with m.If(d_cr.req): # request for regfile access being made
 513             comb += self.cr_r.ren.eq(0b11111111) # enable all
 514         d_cr_delay  = Signal()
 515         sync += d_cr_delay.eq(d_cr.req)
 516         with m.If(d_cr_delay):
 517             # data arrives one clock later
 518             comb += d_cr.data.eq(self.cr_r.data_o)
 519             comb += d_cr.ack.eq(1)
 520
 521         # aaand XER...
 522         with m.If(d_xer.req): # request for regfile access being made
 523             comb += self.xer_r.ren.eq(0b111111) # enable all
 524         d_xer_delay  = Signal()
 525         sync += d_xer_delay.eq(d_xer.req)
 526         with m.If(d_xer_delay):
 527             # data arrives one clock later
 528             comb += d_xer.data.eq(self.xer_r.data_o)
 529             comb += d_xer.ack.eq(1)
 530
 531         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 532         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 533         self.tb_dec_fsm(m, cur_state.dec)
 534
 535         return m
 536
 537     def tb_dec_fsm(self, m, spr_dec):
 538         """tb_dec_fsm
 539
 540         this is a FSM for updating either dec or tb.  it runs alternately
 541         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 542         value to DEC, however the regfile has "passthrough" on it so this
 543         *should* be ok.
 544
 545         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 546         """
 547
 548         comb, sync = m.d.comb, m.d.sync
 549         fast_rf = self.core.regs.rf['fast']
 550         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 551         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 552
 553         with m.FSM() as fsm:
 554
 555             # initiates read of current DEC
 556             with m.State("DEC_READ"):
 557                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 558                 comb += fast_r_dectb.ren.eq(1)
 559                 m.next = "DEC_WRITE"
 560
 561             # waits for DEC read to arrive (1 cycle), updates with new value
 562             with m.State("DEC_WRITE"):
 563                 new_dec = Signal(64)
 564                 # TODO: MSR.LPCR 32-bit decrement mode
 565                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 566                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 567                 comb += fast_w_dectb.wen.eq(1)
 568                 comb += fast_w_dectb.data_i.eq(new_dec)
 569                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 570                 m.next = "TB_READ"
 571
 572             # initiates read of current TB
 573             with m.State("TB_READ"):
 574                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 575                 comb += fast_r_dectb.ren.eq(1)
 576                 m.next = "TB_WRITE"
 577
 578             # waits for read TB to arrive, initiates write of current TB
 579             with m.State("TB_WRITE"):
 580                 new_tb = Signal(64)
 581                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 582                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 583                 comb += fast_w_dectb.wen.eq(1)
 584                 comb += fast_w_dectb.data_i.eq(new_tb)
 585                 m.next = "DEC_READ"
 586
 587         return m
 588
 589     def __iter__(self):
 590         yield from self.pc_i.ports()
 591         yield self.pc_o
 592         yield self.memerr_o
 593         yield from self.core.ports()
 594         yield from self.imem.ports()
 595         yield self.core_bigendian_i
 596         yield self.busy_o
 597
 598     def ports(self):
 599         return list(self)
 600
 601     def external_ports(self):
 602         ports = self.pc_i.ports()
 603         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 604                 ]
 605
 606         if self.jtag_en:
 607             ports += list(self.jtag.external_ports())
 608         else:
 609             # don't add DMI if JTAG is enabled
 610             ports += list(self.dbg.dmi.ports())
 611
 612         ports += list(self.imem.ibus.fields.values())
 613         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 614
 615         if self.sram4x4k:
 616             for sram in self.sram4k:
 617                 ports += list(sram.bus.fields.values())
 618
 619         if self.xics:
 620             ports += list(self.xics_icp.bus.fields.values())
 621             ports += list(self.xics_ics.bus.fields.values())
 622             ports.append(self.int_level_i)
 623
 624         if self.gpio:
 625             ports += list(self.simple_gpio.bus.fields.values())
 626             ports.append(self.gpio_o)
 627
 628         return ports
 629
 630     def ports(self):
 631         return list(self)
 632
 633
 634 class TestIssuer(Elaboratable):
 635     def __init__(self, pspec):
 636         self.ti = TestIssuerInternal(pspec)
 637
 638         self.pll = DummyPLL()
 639
 640         # PLL direct clock or not
 641         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 642         if self.pll_en:
 643             self.pll_18_o = Signal(reset_less=True)
 644
 645     def elaborate(self, platform):
 646         m = Module()
 647         comb = m.d.comb
 648
 649         # TestIssuer runs at direct clock
 650         m.submodules.ti = ti = self.ti
 651         cd_int = ClockDomain("coresync")
 652
 653         if self.pll_en:
 654             # ClockSelect runs at PLL output internal clock rate
 655             m.submodules.pll = pll = self.pll
 656
 657             # add clock domains from PLL
 658             cd_pll = ClockDomain("pllclk")
 659             m.domains += cd_pll
 660
 661             # PLL clock established.  has the side-effect of running clklsel
 662             # at the PLL's speed (see DomainRenamer("pllclk") above)
 663             pllclk = ClockSignal("pllclk")
 664             comb += pllclk.eq(pll.clk_pll_o)
 665
 666             # wire up external 24mhz to PLL
 667             comb += pll.clk_24_i.eq(ClockSignal())
 668
 669             # output 18 mhz PLL test signal
 670             comb += self.pll_18_o.eq(pll.pll_18_o)
 671
 672             # now wire up ResetSignals.  don't mind them being in this domain
 673             pll_rst = ResetSignal("pllclk")
 674             comb += pll_rst.eq(ResetSignal())
 675
 676         # internal clock is set to selector clock-out.  has the side-effect of
 677         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 678         intclk = ClockSignal("coresync")
 679         if self.pll_en:
 680             comb += intclk.eq(pll.clk_pll_o)
 681         else:
 682             comb += intclk.eq(ClockSignal())
 683
 684         return m
 685
 686     def ports(self):
 687         return list(self.ti.ports()) + list(self.pll.ports()) + \
 688                [ClockSignal(), ResetSignal()]
 689
 690     def external_ports(self):
 691         ports = self.ti.external_ports()
 692         ports.append(ClockSignal())
 693         ports.append(ResetSignal())
 694         if self.pll_en:
 695             ports.append(self.pll.clk_sel_i)
 696             ports.append(self.pll_18_o)
 697             ports.append(self.pll.pll_lck_o)
 698         return ports
 699
 700
 701 if __name__ == '__main__':
 702     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 703              'spr': 1,
 704              'div': 1,
 705              'mul': 1,
 706              'shiftrot': 1
 707             }
 708     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 709                          imem_ifacetype='bare_wb',
 710                          addr_wid=48,
 711                          mask_wid=8,
 712                          reg_wid=64,
 713                          units=units)
 714     dut = TestIssuer(pspec)
 715     vl = main(dut, ports=dut.ports(), name="test_issuer")
 716
 717     if len(sys.argv) == 1:
 718         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 719         with open("test_issuer.il", "w") as f:
 720             f.write(vl)