src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
  89
  90         # add interrupt controller?
  91         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  92         if self.xics:
  93             self.xics_icp = XICS_ICP()
  94             self.xics_ics = XICS_ICS()
  95             self.int_level_i = self.xics_ics.int_level_i
  96
  97         # add GPIO peripheral?
  98         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
  99         if self.gpio:
 100             self.simple_gpio = SimpleGPIO()
 101             self.gpio_o = self.simple_gpio.gpio_o
 102
 103         # main instruction core25
 104         self.core = core = NonProductionCore(pspec)
 105
 106         # instruction decoder.  goes into Trap Record
 107         pdecode = create_pdecode()
 108         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 109         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 110                                      opkls=IssuerDecode2ToOperand)
 111         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 112
 113         # Test Instruction memory
 114         self.imem = ConfigFetchUnit(pspec).fu
 115         # one-row cache of instruction read
 116         self.iline = Signal(64) # one instruction line
 117         self.iprev_adr = Signal(64) # previous address: if different, do read
 118
 119         # DMI interface
 120         self.dbg = CoreDebug()
 121
 122         # instruction go/monitor
 123         self.pc_o = Signal(64, reset_less=True)
 124         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 125         self.core_bigendian_i = Signal()
 126         self.busy_o = Signal(reset_less=True)
 127         self.memerr_o = Signal(reset_less=True)
 128
 129         # STATE regfile read /write ports for PC, MSR, SVSTATE
 130         staterf = self.core.regs.rf['state']
 131         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 132         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 133         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 134         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 135         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 136
 137         # DMI interface access
 138         intrf = self.core.regs.rf['int']
 139         crrf = self.core.regs.rf['cr']
 140         xerrf = self.core.regs.rf['xer']
 141         self.int_r = intrf.r_ports['dmi'] # INT read
 142         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 143         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 144
 145         # hack method of keeping an eye on whether branch/trap set the PC
 146         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 147         self.state_nia.wen.name = 'state_nia_wen'
 148
 149     def fetch_fsm(self, m, core, dbg, pc, pc_changed, insn_done,
 150                         core_rst, cur_state,
 151                         fetch_pc_ready_o, fetch_pc_valid_i,
 152                         fetch_insn_valid_o, fetch_insn_ready_i):
 153         """fetch FSM
 154         this FSM performs fetch of raw instruction data, partial-decodes
 155         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 156         read a 2nd 32-bit quantity if that occurs.
 157         """
 158         comb = m.d.comb
 159         sync = m.d.sync
 160         pdecode2 = self.pdecode2
 161         svp64 = self.svp64
 162
 163         # latches copy of raw fetched instruction
 164         fetch_insn_o = Signal(32, reset_less=True)
 165         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 166         sync += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
 167
 168         msr_read = Signal(reset=1)
 169         sv_read = Signal(reset=1)
 170
 171         # address of the next instruction, in the absence of a branch
 172         # depends on the instruction size
 173         nia = Signal(64, reset_less=True)
 174
 175         with m.FSM(name='fetch_fsm'):
 176
 177             # waiting (zzz)
 178             with m.State("IDLE"):
 179                 with m.If(~dbg.core_stop_o & ~core_rst):
 180                     comb += fetch_pc_ready_o.eq(1)
 181                     with m.If(fetch_pc_valid_i):
 182                         # instruction allowed to go: start by reading the PC
 183                         # capture the PC and also drop it into Insn Memory
 184                         # we have joined a pair of combinatorial memory
 185                         # lookups together.  this is Generally Bad.
 186                         comb += self.imem.a_pc_i.eq(pc)
 187                         comb += self.imem.a_valid_i.eq(1)
 188                         comb += self.imem.f_valid_i.eq(1)
 189                         sync += cur_state.pc.eq(pc)
 190
 191                         # initiate read of MSR/SVSTATE. arrives one clock later
 192                         comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 193                         comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 194                         sync += msr_read.eq(0)
 195                         sync += sv_read.eq(0)
 196
 197                         m.next = "INSN_READ"  # move to "wait for bus" phase
 198                 with m.Else():
 199                     comb += core.core_stopped_i.eq(1)
 200                     comb += dbg.core_stopped_i.eq(1)
 201
 202             # dummy pause to find out why simulation is not keeping up
 203             with m.State("INSN_READ"):
 204                 # one cycle later, msr/sv read arrives.  valid only once.
 205                 with m.If(~msr_read):
 206                     sync += msr_read.eq(1) # yeah don't read it again
 207                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 208                 with m.If(~sv_read):
 209                     sync += sv_read.eq(1) # yeah don't read it again
 210                     sync += cur_state.svstate.eq(self.state_r_sv.data_o)
 211                 with m.If(self.imem.f_busy_o): # zzz...
 212                     # busy: stay in wait-read
 213                     comb += self.imem.a_valid_i.eq(1)
 214                     comb += self.imem.f_valid_i.eq(1)
 215                 with m.Else():
 216                     # not busy: instruction fetched
 217                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 218                     # decode the SVP64 prefix, if any
 219                     comb += svp64.raw_opcode_in.eq(insn)
 220                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 221                     # pass the decoded prefix (if any) to PowerDecoder2
 222                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 223                     # calculate the address of the following instruction
 224                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 225                     sync += nia.eq(cur_state.pc + insn_size)
 226                     with m.If(~svp64.is_svp64_mode):
 227                         # with no prefix, store the instruction
 228                         # and hand it directly to the next FSM
 229                         comb += fetch_insn_o.eq(insn)
 230                         m.next = "INSN_READY"
 231                     with m.Else():
 232                         # fetch the rest of the instruction from memory
 233                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 234                         comb += self.imem.a_valid_i.eq(1)
 235                         comb += self.imem.f_valid_i.eq(1)
 236                         m.next = "INSN_READ2"
 237
 238             with m.State("INSN_READ2"):
 239                 with m.If(self.imem.f_busy_o):  # zzz...
 240                     # busy: stay in wait-read
 241                     comb += self.imem.a_valid_i.eq(1)
 242                     comb += self.imem.f_valid_i.eq(1)
 243                 with m.Else():
 244                     # not busy: instruction fetched
 245                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 246                     comb += fetch_insn_o.eq(insn)
 247                     m.next = "INSN_READY"
 248
 249             with m.State("INSN_READY"):
 250                 # hand over the instruction, to be decoded
 251                 comb += fetch_insn_valid_o.eq(1)
 252                 with m.If(fetch_insn_ready_i):
 253                     m.next = "IDLE"
 254
 255         # code-morph: moving the actual PC-setting out of "execute"
 256         # so that it's easier to move this into an "issue" FSM.
 257
 258         # ok here we are not reading the branch unit.  TODO
 259         # this just blithely overwrites whatever pipeline
 260         # updated the PC
 261         core_busy_o = core.busy_o                 # core is busy
 262         with m.If(insn_done & (~pc_changed) & (~core_busy_o)):
 263             comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
 264             comb += self.state_w_pc.data_i.eq(nia)
 265
 266     def issue_fsm(self, m, core, cur_state, pc_changed, sv_changed,
 267                   fetch_pc_ready_o, fetch_pc_valid_i,
 268                   fetch_insn_valid_o, fetch_insn_ready_i,
 269                   exec_insn_valid_i, exec_insn_ready_o,
 270                   exec_pc_valid_o, exec_pc_ready_i):
 271         """issue FSM
 272
 273         decode / issue FSM.  this interacts with the "fetch" FSM
 274         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 275         (outgoing). also interacts with the "execute" FSM
 276         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 277         (incoming).
 278         SVP64 RM prefixes have already been set up by the
 279         "fetch" phase, so execute is fairly straightforward.
 280         """
 281
 282         comb = m.d.comb
 283         sync = m.d.sync
 284         pdecode2 = self.pdecode2
 285
 286         # temporaries
 287         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 288
 289         # for updating svstate (things like srcstep etc.)
 290         update_svstate = Signal() # set this (below) if updating
 291         new_svstate = SVSTATERec("new_svstate")
 292         comb += new_svstate.eq(cur_state.svstate)
 293
 294         with m.FSM(name="issue_fsm"):
 295
 296             # go fetch the instruction at the current PC
 297             # at this point, there is no instruction running, that
 298             # could inadvertently update the PC.
 299             with m.State("INSN_FETCH"):
 300                 # TODO: update PC here, before fetch
 301                 comb += fetch_pc_valid_i.eq(1)
 302                 with m.If(fetch_pc_ready_o):
 303                     m.next = "INSN_WAIT"
 304
 305             # decode the instruction when it arrives
 306             with m.State("INSN_WAIT"):
 307                 comb += fetch_insn_ready_i.eq(1)
 308                 with m.If(fetch_insn_valid_o):
 309                     # decode the instruction
 310                     sync += core.e.eq(pdecode2.e)
 311                     sync += core.state.eq(cur_state)
 312                     sync += core.raw_insn_i.eq(dec_opcode_i)
 313                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 314                     # TODO: loop into INSN_FETCH if it's a vector instruction
 315                     #       and VL == 0.  this because VL==0 is a for-loop
 316                     #       from 0 to 0 i.e. always, always a NOP.
 317                     m.next = "INSN_EXECUTE"  # move to "execute"
 318
 319             with m.State("INSN_EXECUTE"):
 320                 comb += exec_insn_valid_i.eq(1)
 321                 with m.If(exec_insn_ready_o):
 322                     m.next = "EXECUTE_WAIT"
 323
 324             with m.State("EXECUTE_WAIT"):
 325                 comb += exec_pc_ready_i.eq(1)
 326                 with m.If(exec_pc_valid_o):
 327                     # TODO: update SRCSTEP here (in new_svstate)
 328                     #       and set update_svstate to True *as long as*
 329                     #       PC / SVSTATE was not modified.  that's an
 330                     #       exception (or setvl was called)
 331                     # TODO: loop into INSN_EXECUTE if it's a vector instruction
 332                     #       and SRCSTEP != VL-1 and PowerDecoder.no_out_vec
 333                     #       is True
 334                     #       unless PC / SVSTATE was modified, in that case do
 335                     #       go back to INSN_FETCH.
 336                     m.next = "INSN_FETCH"
 337
 338         # check if svstate needs updating: if so, write it to State Regfile
 339         with m.If(update_svstate):
 340             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 341             comb += self.state_w_sv.data_i.eq(new_svstate)
 342             sync += cur_state.svstate.eq(new_svstate) # for next clock
 343
 344     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 345                     exec_insn_valid_i, exec_insn_ready_o,
 346                     exec_pc_valid_o, exec_pc_ready_i):
 347         """execute FSM
 348
 349         execute FSM. this interacts with the "issue" FSM
 350         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 351         (outgoing). SVP64 RM prefixes have already been set up by the
 352         "issue" phase, so execute is fairly straightforward.
 353         """
 354
 355         comb = m.d.comb
 356         sync = m.d.sync
 357         pdecode2 = self.pdecode2
 358         svp64 = self.svp64
 359
 360         # temporaries
 361         core_busy_o = core.busy_o                 # core is busy
 362         core_ivalid_i = core.ivalid_i             # instruction is valid
 363         core_issue_i = core.issue_i               # instruction is issued
 364         insn_type = core.e.do.insn_type           # instruction MicroOp type
 365
 366         with m.FSM(name="exec_fsm"):
 367
 368             # waiting for instruction bus (stays there until not busy)
 369             with m.State("INSN_START"):
 370                 comb += exec_insn_ready_o.eq(1)
 371                 with m.If(exec_insn_valid_i):
 372                     comb += core_ivalid_i.eq(1)  # instruction is valid
 373                     comb += core_issue_i.eq(1)  # and issued
 374                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 375
 376             # instruction started: must wait till it finishes
 377             with m.State("INSN_ACTIVE"):
 378                 with m.If(insn_type != MicrOp.OP_NOP):
 379                     comb += core_ivalid_i.eq(1) # instruction is valid
 380                 # note changes to PC and SVSTATE
 381                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 382                     sync += sv_changed.eq(1)
 383                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 384                     sync += pc_changed.eq(1)
 385                 with m.If(~core_busy_o): # instruction done!
 386                     comb += insn_done.eq(1)
 387                     sync += core.e.eq(0)
 388                     sync += core.raw_insn_i.eq(0)
 389                     sync += core.bigendian_i.eq(0)
 390                     sync += sv_changed.eq(0)
 391                     sync += pc_changed.eq(0)
 392                     comb += exec_pc_valid_o.eq(1)
 393                     with m.If(exec_pc_ready_i):
 394                         m.next = "INSN_START"  # back to fetch
 395
 396     def elaborate(self, platform):
 397         m = Module()
 398         comb, sync = m.d.comb, m.d.sync
 399
 400         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 401         m.submodules.imem = imem = self.imem
 402         m.submodules.dbg = dbg = self.dbg
 403         if self.jtag_en:
 404             m.submodules.jtag = jtag = self.jtag
 405             # TODO: UART2GDB mux, here, from external pin
 406             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 407             sync += dbg.dmi.connect_to(jtag.dmi)
 408
 409         cur_state = self.cur_state
 410
 411         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 412         if self.sram4x4k:
 413             for i, sram in enumerate(self.sram4k):
 414                 m.submodules["sram4k_%d" % i] = sram
 415                 comb += sram.enable.eq(self.wb_sram_en)
 416
 417         # XICS interrupt handler
 418         if self.xics:
 419             m.submodules.xics_icp = icp = self.xics_icp
 420             m.submodules.xics_ics = ics = self.xics_ics
 421             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 422             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 423
 424         # GPIO test peripheral
 425         if self.gpio:
 426             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 427
 428         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 429         # XXX causes litex ECP5 test to get wrong idea about input and output
 430         # (but works with verilator sim *sigh*)
 431         #if self.gpio and self.xics:
 432         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 433
 434         # instruction decoder
 435         pdecode = create_pdecode()
 436         m.submodules.dec2 = pdecode2 = self.pdecode2
 437         m.submodules.svp64 = svp64 = self.svp64
 438
 439         # convenience
 440         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 441         intrf = self.core.regs.rf['int']
 442
 443         # clock delay power-on reset
 444         cd_por  = ClockDomain(reset_less=True)
 445         cd_sync = ClockDomain()
 446         core_sync = ClockDomain("coresync")
 447         m.domains += cd_por, cd_sync, core_sync
 448
 449         ti_rst = Signal(reset_less=True)
 450         delay = Signal(range(4), reset=3)
 451         with m.If(delay != 0):
 452             m.d.por += delay.eq(delay - 1)
 453         comb += cd_por.clk.eq(ClockSignal())
 454
 455         # power-on reset delay
 456         core_rst = ResetSignal("coresync")
 457         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 458         comb += core_rst.eq(ti_rst)
 459
 460         # busy/halted signals from core
 461         comb += self.busy_o.eq(core.busy_o)
 462         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 463
 464         # temporary hack: says "go" immediately for both address gen and ST
 465         l0 = core.l0
 466         ldst = core.fus.fus['ldst0']
 467         st_go_edge = rising_edge(m, ldst.st.rel_o)
 468         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 469         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 470
 471         # PC and instruction from I-Memory
 472         comb += self.pc_o.eq(cur_state.pc)
 473         pc_changed = Signal() # note write to PC
 474         sv_changed = Signal() # note write to SVSTATE
 475         insn_done = Signal()  # fires just once
 476
 477         # read the PC
 478         pc = Signal(64, reset_less=True)
 479         pc_ok_delay = Signal()
 480         sync += pc_ok_delay.eq(~self.pc_i.ok)
 481         with m.If(self.pc_i.ok):
 482             # incoming override (start from pc_i)
 483             comb += pc.eq(self.pc_i.data)
 484         with m.Else():
 485             # otherwise read StateRegs regfile for PC...
 486             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 487         # ... but on a 1-clock delay
 488         with m.If(pc_ok_delay):
 489             comb += pc.eq(self.state_r_pc.data_o)
 490
 491         # don't write pc every cycle
 492         comb += self.state_w_pc.wen.eq(0)
 493         comb += self.state_w_pc.data_i.eq(0)
 494
 495         # don't read msr or svstate every cycle
 496         comb += self.state_r_sv.ren.eq(0)
 497         comb += self.state_r_msr.ren.eq(0)
 498
 499         # connect up debug signals
 500         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 501         comb += dbg.terminate_i.eq(core.core_terminate_o)
 502         comb += dbg.state.pc.eq(pc)
 503         #comb += dbg.state.pc.eq(cur_state.pc)
 504         comb += dbg.state.msr.eq(cur_state.msr)
 505
 506         # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
 507         # these are the handshake signals between fetch and decode/execute
 508
 509         # fetch FSM can run as soon as the PC is valid
 510         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 511         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 512
 513         # fetch FSM hands over the instruction to be decoded / issued
 514         fetch_insn_valid_o = Signal()
 515         fetch_insn_ready_i = Signal()
 516
 517         # issue FSM delivers the instruction to the be executed
 518         exec_insn_valid_i = Signal()
 519         exec_insn_ready_o = Signal()
 520
 521         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 522         exec_pc_valid_o = Signal()
 523         exec_pc_ready_i = Signal()
 524
 525         # actually use a nmigen FSM for the first time (w00t)
 526         # this FSM is perhaps unusual in that it detects conditions
 527         # then "holds" information, combinatorially, for the core
 528         # (as opposed to using sync - which would be on a clock's delay)
 529         # this includes the actual opcode, valid flags and so on.
 530
 531         self.fetch_fsm(m, core, dbg, pc, pc_changed, insn_done,
 532                        core_rst, cur_state,
 533                        fetch_pc_ready_o, fetch_pc_valid_i,
 534                        fetch_insn_valid_o, fetch_insn_ready_i)
 535
 536         # TODO: an SVSTATE-based for-loop FSM that goes in between
 537         # fetch pc/insn ready/valid and advances SVSTATE.srcstep
 538         # until it reaches VL-1 or PowerDecoder2.no_out_vec is True.
 539         self.issue_fsm(m, core, cur_state, pc_changed, sv_changed,
 540                        fetch_pc_ready_o, fetch_pc_valid_i,
 541                        fetch_insn_valid_o, fetch_insn_ready_i,
 542                        exec_insn_valid_i, exec_insn_ready_o,
 543                        exec_pc_ready_i, exec_pc_valid_o)
 544
 545         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 546                          exec_insn_valid_i, exec_insn_ready_o,
 547                          exec_pc_ready_i, exec_pc_valid_o)
 548
 549         # this bit doesn't have to be in the FSM: connect up to read
 550         # regfiles on demand from DMI
 551         with m.If(d_reg.req): # request for regfile access being made
 552             # TODO: error-check this
 553             # XXX should this be combinatorial?  sync better?
 554             if intrf.unary:
 555                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 556             else:
 557                 comb += self.int_r.addr.eq(d_reg.addr)
 558                 comb += self.int_r.ren.eq(1)
 559         d_reg_delay  = Signal()
 560         sync += d_reg_delay.eq(d_reg.req)
 561         with m.If(d_reg_delay):
 562             # data arrives one clock later
 563             comb += d_reg.data.eq(self.int_r.data_o)
 564             comb += d_reg.ack.eq(1)
 565
 566         # sigh same thing for CR debug
 567         with m.If(d_cr.req): # request for regfile access being made
 568             comb += self.cr_r.ren.eq(0b11111111) # enable all
 569         d_cr_delay  = Signal()
 570         sync += d_cr_delay.eq(d_cr.req)
 571         with m.If(d_cr_delay):
 572             # data arrives one clock later
 573             comb += d_cr.data.eq(self.cr_r.data_o)
 574             comb += d_cr.ack.eq(1)
 575
 576         # aaand XER...
 577         with m.If(d_xer.req): # request for regfile access being made
 578             comb += self.xer_r.ren.eq(0b111111) # enable all
 579         d_xer_delay  = Signal()
 580         sync += d_xer_delay.eq(d_xer.req)
 581         with m.If(d_xer_delay):
 582             # data arrives one clock later
 583             comb += d_xer.data.eq(self.xer_r.data_o)
 584             comb += d_xer.ack.eq(1)
 585
 586         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 587         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 588         self.tb_dec_fsm(m, cur_state.dec)
 589
 590         return m
 591
 592     def tb_dec_fsm(self, m, spr_dec):
 593         """tb_dec_fsm
 594
 595         this is a FSM for updating either dec or tb.  it runs alternately
 596         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 597         value to DEC, however the regfile has "passthrough" on it so this
 598         *should* be ok.
 599
 600         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 601         """
 602
 603         comb, sync = m.d.comb, m.d.sync
 604         fast_rf = self.core.regs.rf['fast']
 605         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 606         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 607
 608         with m.FSM() as fsm:
 609
 610             # initiates read of current DEC
 611             with m.State("DEC_READ"):
 612                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 613                 comb += fast_r_dectb.ren.eq(1)
 614                 m.next = "DEC_WRITE"
 615
 616             # waits for DEC read to arrive (1 cycle), updates with new value
 617             with m.State("DEC_WRITE"):
 618                 new_dec = Signal(64)
 619                 # TODO: MSR.LPCR 32-bit decrement mode
 620                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 621                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 622                 comb += fast_w_dectb.wen.eq(1)
 623                 comb += fast_w_dectb.data_i.eq(new_dec)
 624                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 625                 m.next = "TB_READ"
 626
 627             # initiates read of current TB
 628             with m.State("TB_READ"):
 629                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 630                 comb += fast_r_dectb.ren.eq(1)
 631                 m.next = "TB_WRITE"
 632
 633             # waits for read TB to arrive, initiates write of current TB
 634             with m.State("TB_WRITE"):
 635                 new_tb = Signal(64)
 636                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 637                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 638                 comb += fast_w_dectb.wen.eq(1)
 639                 comb += fast_w_dectb.data_i.eq(new_tb)
 640                 m.next = "DEC_READ"
 641
 642         return m
 643
 644     def __iter__(self):
 645         yield from self.pc_i.ports()
 646         yield self.pc_o
 647         yield self.memerr_o
 648         yield from self.core.ports()
 649         yield from self.imem.ports()
 650         yield self.core_bigendian_i
 651         yield self.busy_o
 652
 653     def ports(self):
 654         return list(self)
 655
 656     def external_ports(self):
 657         ports = self.pc_i.ports()
 658         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 659                 ]
 660
 661         if self.jtag_en:
 662             ports += list(self.jtag.external_ports())
 663         else:
 664             # don't add DMI if JTAG is enabled
 665             ports += list(self.dbg.dmi.ports())
 666
 667         ports += list(self.imem.ibus.fields.values())
 668         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 669
 670         if self.sram4x4k:
 671             for sram in self.sram4k:
 672                 ports += list(sram.bus.fields.values())
 673
 674         if self.xics:
 675             ports += list(self.xics_icp.bus.fields.values())
 676             ports += list(self.xics_ics.bus.fields.values())
 677             ports.append(self.int_level_i)
 678
 679         if self.gpio:
 680             ports += list(self.simple_gpio.bus.fields.values())
 681             ports.append(self.gpio_o)
 682
 683         return ports
 684
 685     def ports(self):
 686         return list(self)
 687
 688
 689 class TestIssuer(Elaboratable):
 690     def __init__(self, pspec):
 691         self.ti = TestIssuerInternal(pspec)
 692
 693         self.pll = DummyPLL()
 694
 695         # PLL direct clock or not
 696         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 697         if self.pll_en:
 698             self.pll_18_o = Signal(reset_less=True)
 699
 700     def elaborate(self, platform):
 701         m = Module()
 702         comb = m.d.comb
 703
 704         # TestIssuer runs at direct clock
 705         m.submodules.ti = ti = self.ti
 706         cd_int = ClockDomain("coresync")
 707
 708         if self.pll_en:
 709             # ClockSelect runs at PLL output internal clock rate
 710             m.submodules.pll = pll = self.pll
 711
 712             # add clock domains from PLL
 713             cd_pll = ClockDomain("pllclk")
 714             m.domains += cd_pll
 715
 716             # PLL clock established.  has the side-effect of running clklsel
 717             # at the PLL's speed (see DomainRenamer("pllclk") above)
 718             pllclk = ClockSignal("pllclk")
 719             comb += pllclk.eq(pll.clk_pll_o)
 720
 721             # wire up external 24mhz to PLL
 722             comb += pll.clk_24_i.eq(ClockSignal())
 723
 724             # output 18 mhz PLL test signal
 725             comb += self.pll_18_o.eq(pll.pll_18_o)
 726
 727             # now wire up ResetSignals.  don't mind them being in this domain
 728             pll_rst = ResetSignal("pllclk")
 729             comb += pll_rst.eq(ResetSignal())
 730
 731         # internal clock is set to selector clock-out.  has the side-effect of
 732         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 733         intclk = ClockSignal("coresync")
 734         if self.pll_en:
 735             comb += intclk.eq(pll.clk_pll_o)
 736         else:
 737             comb += intclk.eq(ClockSignal())
 738
 739         return m
 740
 741     def ports(self):
 742         return list(self.ti.ports()) + list(self.pll.ports()) + \
 743                [ClockSignal(), ResetSignal()]
 744
 745     def external_ports(self):
 746         ports = self.ti.external_ports()
 747         ports.append(ClockSignal())
 748         ports.append(ResetSignal())
 749         if self.pll_en:
 750             ports.append(self.pll.clk_sel_i)
 751             ports.append(self.pll_18_o)
 752             ports.append(self.pll.pll_lck_o)
 753         return ports
 754
 755
 756 if __name__ == '__main__':
 757     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 758              'spr': 1,
 759              'div': 1,
 760              'mul': 1,
 761              'shiftrot': 1
 762             }
 763     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 764                          imem_ifacetype='bare_wb',
 765                          addr_wid=48,
 766                          mask_wid=8,
 767                          reg_wid=64,
 768                          units=units)
 769     dut = TestIssuer(pspec)
 770     vl = main(dut, ports=dut.ports(), name="test_issuer")
 771
 772     if len(sys.argv) == 1:
 773         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 774         with open("test_issuer.il", "w") as f:
 775             f.write(vl)