3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
41 from soc
.clock
.select
import ClockSelect
42 from soc
.clock
.dummypll
import DummyPLL
43 from soc
.sv
.svstate
import SVSTATERec
46 from nmutil
.util
import rising_edge
48 def get_insn(f_instr_o
, pc
):
49 if f_instr_o
.width
== 32:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o
.word_select(pc
[2], 32)
55 # gets state input or reads from state regfile
56 def state_get(m
, state_i
, name
, regfile
, regnum
):
60 res
= Signal(64, reset_less
=True, name
=name
)
61 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
62 sync
+= res_ok_delay
.eq(~state_i
.ok
)
63 with m
.If(state_i
.ok
):
64 # incoming override (start from pc_i)
65 comb
+= res
.eq(state_i
.data
)
67 # otherwise read StateRegs regfile for PC...
68 comb
+= regfile
.ren
.eq(1<<regnum
)
69 # ... but on a 1-clock delay
70 with m
.If(res_ok_delay
):
71 comb
+= res
.eq(regfile
.data_o
)
74 def get_predint(m
, mask
):
75 """decode SVP64 predicate integer mask field to reg number and invert
76 this is identical to the equivalent function in ISACaller except that
77 it doesn't read the INT directly, it just decodes "what needs to be done"
78 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
84 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
87 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
90 with m
.Case(SVP64PredInt
.R3
.value
):
92 with m
.Case(SVP64PredInt
.R3_N
.value
):
95 with m
.Case(SVP64PredInt
.R10
.value
):
96 comb
+= regread
.eq(10)
97 with m
.Case(SVP64PredInt
.R10_N
.value
):
98 comb
+= regread
.eq(10)
100 with m
.Case(SVP64PredInt
.R30
.value
):
101 comb
+= regread
.eq(30)
102 with m
.Case(SVP64PredInt
.R30_N
.value
):
103 comb
+= regread
.eq(30)
105 return regread
, invert
, unary
107 def get_predcr(m
, mask
):
108 """decode SVP64 predicate CR to reg number field and invert status
109 this is identical to _get_predcr in ISACaller
114 with m
.Case(SVP64PredCR
.LT
.value
):
117 with m
.Case(SVP64PredCR
.GE
.value
):
120 with m
.Case(SVP64PredCR
.GT
.value
):
123 with m
.Case(SVP64PredCR
.LE
.value
):
126 with m
.Case(SVP64PredCR
.EQ
.value
):
129 with m
.Case(SVP64PredCR
.NE
.value
):
132 with m
.Case(SVP64PredCR
.SO
.value
):
135 with m
.Case(SVP64PredCR
.NS
.value
):
141 class TestIssuerInternal(Elaboratable
):
142 """TestIssuer - reads instructions from TestMemory and issues them
144 efficiency and speed is not the main goal here: functional correctness
145 and code clarity is. optimisations (which almost 100% interfere with
146 easy understanding) come later.
148 def __init__(self
, pspec
):
150 # test is SVP64 is to be enabled
151 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
153 # JTAG interface. add this right at the start because if it's
154 # added it *modifies* the pspec, by adding enable/disable signals
155 # for parts of the rest of the core
156 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
158 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
160 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
161 # add signals to pspec to enable/disable icache and dcache
162 # (or data and intstruction wishbone if icache/dcache not included)
163 # https://bugs.libre-soc.org/show_bug.cgi?id=520
164 # TODO: do we actually care if these are not domain-synchronised?
165 # honestly probably not.
166 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
167 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
168 self
.wb_sram_en
= self
.jtag
.wb_sram_en
170 self
.wb_sram_en
= Const(1)
172 # add 4k sram blocks?
173 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
174 pspec
.sram4x4kblock
== True)
178 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
181 # add interrupt controller?
182 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
184 self
.xics_icp
= XICS_ICP()
185 self
.xics_ics
= XICS_ICS()
186 self
.int_level_i
= self
.xics_ics
.int_level_i
188 # add GPIO peripheral?
189 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
191 self
.simple_gpio
= SimpleGPIO()
192 self
.gpio_o
= self
.simple_gpio
.gpio_o
194 # main instruction core. suitable for prototyping / demo only
195 self
.core
= core
= NonProductionCore(pspec
)
197 # instruction decoder. goes into Trap Record
198 pdecode
= create_pdecode()
199 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
200 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
201 opkls
=IssuerDecode2ToOperand
,
202 svp64_en
=self
.svp64_en
)
204 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
206 # Test Instruction memory
207 self
.imem
= ConfigFetchUnit(pspec
).fu
210 self
.dbg
= CoreDebug()
212 # instruction go/monitor
213 self
.pc_o
= Signal(64, reset_less
=True)
214 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
215 self
.svstate_i
= Data(32, "svstate_i") # ditto
216 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
217 self
.busy_o
= Signal(reset_less
=True)
218 self
.memerr_o
= Signal(reset_less
=True)
220 # STATE regfile read /write ports for PC, MSR, SVSTATE
221 staterf
= self
.core
.regs
.rf
['state']
222 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
223 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
224 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
225 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
226 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
228 # DMI interface access
229 intrf
= self
.core
.regs
.rf
['int']
230 crrf
= self
.core
.regs
.rf
['cr']
231 xerrf
= self
.core
.regs
.rf
['xer']
232 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
233 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
234 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
237 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
238 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
240 # hack method of keeping an eye on whether branch/trap set the PC
241 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
242 self
.state_nia
.wen
.name
= 'state_nia_wen'
244 # pulse to synchronize the simulator at instruction end
245 self
.insn_done
= Signal()
248 # store copies of predicate masks
249 self
.srcmask
= Signal(64)
250 self
.dstmask
= Signal(64)
252 def fetch_fsm(self
, m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
253 fetch_pc_ready_o
, fetch_pc_valid_i
,
254 fetch_insn_valid_o
, fetch_insn_ready_i
):
257 this FSM performs fetch of raw instruction data, partial-decodes
258 it 32-bit at a time to detect SVP64 prefixes, and will optionally
259 read a 2nd 32-bit quantity if that occurs.
263 pdecode2
= self
.pdecode2
264 cur_state
= self
.cur_state
265 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
267 msr_read
= Signal(reset
=1)
269 with m
.FSM(name
='fetch_fsm'):
272 with m
.State("IDLE"):
273 comb
+= fetch_pc_ready_o
.eq(1)
274 with m
.If(fetch_pc_valid_i
):
275 # instruction allowed to go: start by reading the PC
276 # capture the PC and also drop it into Insn Memory
277 # we have joined a pair of combinatorial memory
278 # lookups together. this is Generally Bad.
279 comb
+= self
.imem
.a_pc_i
.eq(pc
)
280 comb
+= self
.imem
.a_valid_i
.eq(1)
281 comb
+= self
.imem
.f_valid_i
.eq(1)
282 sync
+= cur_state
.pc
.eq(pc
)
283 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
285 # initiate read of MSR. arrives one clock later
286 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
287 sync
+= msr_read
.eq(0)
289 m
.next
= "INSN_READ" # move to "wait for bus" phase
291 # dummy pause to find out why simulation is not keeping up
292 with m
.State("INSN_READ"):
293 # one cycle later, msr/sv read arrives. valid only once.
294 with m
.If(~msr_read
):
295 sync
+= msr_read
.eq(1) # yeah don't read it again
296 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
297 with m
.If(self
.imem
.f_busy_o
): # zzz...
298 # busy: stay in wait-read
299 comb
+= self
.imem
.a_valid_i
.eq(1)
300 comb
+= self
.imem
.f_valid_i
.eq(1)
302 # not busy: instruction fetched
303 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
306 # decode the SVP64 prefix, if any
307 comb
+= svp64
.raw_opcode_in
.eq(insn
)
308 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
309 # pass the decoded prefix (if any) to PowerDecoder2
310 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
311 # remember whether this is a prefixed instruction, so
312 # the FSM can readily loop when VL==0
313 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
314 # calculate the address of the following instruction
315 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
316 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
317 with m
.If(~svp64
.is_svp64_mode
):
318 # with no prefix, store the instruction
319 # and hand it directly to the next FSM
320 sync
+= dec_opcode_i
.eq(insn
)
321 m
.next
= "INSN_READY"
323 # fetch the rest of the instruction from memory
324 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
325 comb
+= self
.imem
.a_valid_i
.eq(1)
326 comb
+= self
.imem
.f_valid_i
.eq(1)
327 m
.next
= "INSN_READ2"
329 # not SVP64 - 32-bit only
330 sync
+= nia
.eq(cur_state
.pc
+ 4)
331 sync
+= dec_opcode_i
.eq(insn
)
332 m
.next
= "INSN_READY"
334 with m
.State("INSN_READ2"):
335 with m
.If(self
.imem
.f_busy_o
): # zzz...
336 # busy: stay in wait-read
337 comb
+= self
.imem
.a_valid_i
.eq(1)
338 comb
+= self
.imem
.f_valid_i
.eq(1)
340 # not busy: instruction fetched
341 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
342 sync
+= dec_opcode_i
.eq(insn
)
343 m
.next
= "INSN_READY"
344 # TODO: probably can start looking at pdecode2.rm_dec
345 # here (or maybe even in INSN_READ state, if svp64_mode
346 # detected, in order to trigger - and wait for - the
348 pmode
= pdecode2
.rm_dec
.predmode
350 if pmode != SVP64PredMode.ALWAYS.value:
351 fire predicate loading FSM and wait before
354 sync += self.srcmask.eq(-1) # set to all 1s
355 sync += self.dstmask.eq(-1) # set to all 1s
356 m.next = "INSN_READY"
359 with m
.State("INSN_READY"):
360 # hand over the instruction, to be decoded
361 comb
+= fetch_insn_valid_o
.eq(1)
362 with m
.If(fetch_insn_ready_i
):
365 def fetch_predicate_fsm(self
, m
,
366 pred_insn_valid_i
, pred_insn_ready_o
,
367 pred_mask_valid_o
, pred_mask_ready_i
):
368 """fetch_predicate_fsm - obtains (constructs in the case of CR)
369 src/dest predicate masks
371 https://bugs.libre-soc.org/show_bug.cgi?id=617
372 the predicates can be read here, by using IntRegs r_ports['pred']
373 or CRRegs r_ports['pred']. in the case of CRs it will have to
374 be done through multiple reads, extracting one relevant at a time.
375 later, a faster way would be to use the 32-bit-wide CR port but
376 this is more complex decoding, here. equivalent code used in
377 ISACaller is "from soc.decoder.isa.caller import get_predcr"
381 pdecode2
= self
.pdecode2
382 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
383 predmode
= rm_dec
.predmode
384 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
385 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
386 # if predmode == INT:
387 # INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
388 # INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
389 # TODO read INT-src and INT-dst into self.srcmask+dstmask
390 # elif predmode == CR:
391 # CR-src sidx, sinvert = get_predcr(m, srcpred)
392 # CR-dst didx, dinvert = get_predcr(m, dstpred)
393 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
395 # sync += self.srcmask.eq(-1) # set to all 1s
396 # sync += self.dstmask.eq(-1) # set to all 1s
397 with m
.FSM(name
="fetch_predicate"):
399 with m
.State("FETCH_PRED_IDLE"):
400 comb
+= pred_insn_ready_o
.eq(1)
401 with m
.If(pred_insn_valid_i
):
402 sync
+= self
.srcmask
.eq(-1)
403 sync
+= self
.dstmask
.eq(-1)
404 m
.next
= "FETCH_PRED_DONE"
406 with m
.State("FETCH_PRED_DONE"):
407 comb
+= pred_mask_valid_o
.eq(1)
408 with m
.If(pred_mask_ready_i
):
409 m
.next
= "FETCH_PRED_IDLE"
411 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
412 dbg
, core_rst
, is_svp64_mode
,
413 fetch_pc_ready_o
, fetch_pc_valid_i
,
414 fetch_insn_valid_o
, fetch_insn_ready_i
,
415 pred_insn_valid_i
, pred_insn_ready_o
,
416 pred_mask_valid_o
, pred_mask_ready_i
,
417 exec_insn_valid_i
, exec_insn_ready_o
,
418 exec_pc_valid_o
, exec_pc_ready_i
):
421 decode / issue FSM. this interacts with the "fetch" FSM
422 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
423 (outgoing). also interacts with the "execute" FSM
424 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
426 SVP64 RM prefixes have already been set up by the
427 "fetch" phase, so execute is fairly straightforward.
432 pdecode2
= self
.pdecode2
433 cur_state
= self
.cur_state
436 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
438 # for updating svstate (things like srcstep etc.)
439 update_svstate
= Signal() # set this (below) if updating
440 new_svstate
= SVSTATERec("new_svstate")
441 comb
+= new_svstate
.eq(cur_state
.svstate
)
443 # precalculate srcstep+1 and dststep+1
444 cur_srcstep
= cur_state
.svstate
.srcstep
445 cur_dststep
= cur_state
.svstate
.dststep
446 next_srcstep
= Signal
.like(cur_srcstep
)
447 next_dststep
= Signal
.like(cur_dststep
)
448 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
449 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
451 with m
.FSM(name
="issue_fsm"):
453 # sync with the "fetch" phase which is reading the instruction
454 # at this point, there is no instruction running, that
455 # could inadvertently update the PC.
456 with m
.State("ISSUE_START"):
457 # wait on "core stop" release, before next fetch
458 # need to do this here, in case we are in a VL==0 loop
459 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
460 comb
+= fetch_pc_valid_i
.eq(1) # tell fetch to start
461 with m
.If(fetch_pc_ready_o
): # fetch acknowledged us
464 # tell core it's stopped, and acknowledge debug handshake
465 comb
+= core
.core_stopped_i
.eq(1)
466 comb
+= dbg
.core_stopped_i
.eq(1)
467 # while stopped, allow updating the PC and SVSTATE
468 with m
.If(self
.pc_i
.ok
):
469 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
470 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
471 sync
+= pc_changed
.eq(1)
472 with m
.If(self
.svstate_i
.ok
):
473 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
474 comb
+= update_svstate
.eq(1)
475 sync
+= sv_changed
.eq(1)
477 # decode the instruction when it arrives
478 with m
.State("INSN_WAIT"):
479 comb
+= fetch_insn_ready_i
.eq(1)
480 with m
.If(fetch_insn_valid_o
):
481 # decode the instruction
482 sync
+= core
.e
.eq(pdecode2
.e
)
483 sync
+= core
.state
.eq(cur_state
)
484 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
485 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
486 # set RA_OR_ZERO detection in satellite decoders
487 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
488 # loop into ISSUE_START if it's a SVP64 instruction
489 # and VL == 0. this because VL==0 is a for-loop
490 # from 0 to 0 i.e. always, always a NOP.
491 cur_vl
= cur_state
.svstate
.vl
492 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
493 # update the PC before fetching the next instruction
494 # since we are in a VL==0 loop, no instruction was
495 # executed that we could be overwriting
496 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
497 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
498 comb
+= self
.insn_done
.eq(1)
499 m
.next
= "ISSUE_START"
501 m
.next
= "PRED_START" # start fetching the predicate
503 with m
.State("PRED_START"):
504 comb
+= pred_insn_valid_i
.eq(1) # tell fetch_pred to start
505 with m
.If(pred_insn_ready_o
): # fetch_pred acknowledged us
508 with m
.State("MASK_WAIT"):
509 comb
+= pred_mask_ready_i
.eq(1) # ready to receive the masks
510 with m
.If(pred_mask_valid_o
): # predication masks are ready
511 m
.next
= "INSN_EXECUTE"
513 # handshake with execution FSM, move to "wait" once acknowledged
514 with m
.State("INSN_EXECUTE"):
515 # with m.If(is_svp64_mode):
516 # TODO advance src/dst step to "skip" over predicated-out
517 # from self.srcmask and self.dstmask
518 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
519 # but still without exceeding VL in either case
520 # IMPORTANT: when changing src/dest step, have to
521 # jump to m.next = "DECODE_SV" to deal with the change in
524 with m
.If(is_svp64_mode
):
526 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
527 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
530 if not pred_src_zero:
531 if (((1<<cur_srcstep) & self.srcmask) == 0) and
533 comb += update_svstate.eq(1)
534 comb += new_svstate.srcstep.eq(next_srcstep)
535 sync += sv_changed.eq(1)
537 if not pred_dst_zero:
538 if (((1<<cur_dststep) & self.dstmask) == 0) and
540 comb += new_svstate.dststep.eq(next_dststep)
541 comb += update_svstate.eq(1)
542 sync += sv_changed.eq(1)
548 comb
+= exec_insn_valid_i
.eq(1) # trigger execute
549 with m
.If(exec_insn_ready_o
): # execute acknowledged us
550 m
.next
= "EXECUTE_WAIT"
552 with m
.State("EXECUTE_WAIT"):
553 # wait on "core stop" release, at instruction end
554 # need to do this here, in case we are in a VL>1 loop
555 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
556 comb
+= exec_pc_ready_i
.eq(1)
557 with m
.If(exec_pc_valid_o
):
559 # was this the last loop iteration?
561 cur_vl
= cur_state
.svstate
.vl
562 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
564 # if either PC or SVSTATE were changed by the previous
565 # instruction, go directly back to Fetch, without
566 # updating either PC or SVSTATE
567 with m
.If(pc_changed | sv_changed
):
568 m
.next
= "ISSUE_START"
570 # also return to Fetch, when no output was a vector
571 # (regardless of SRCSTEP and VL), or when the last
572 # instruction was really the last one of the VL loop
573 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
574 # before going back to fetch, update the PC state
575 # register with the NIA.
576 # ok here we are not reading the branch unit.
577 # TODO: this just blithely overwrites whatever
578 # pipeline updated the PC
579 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
580 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
581 # reset SRCSTEP before returning to Fetch
582 with m
.If(pdecode2
.loop_continue
):
583 comb
+= new_svstate
.srcstep
.eq(0)
584 comb
+= new_svstate
.dststep
.eq(0)
585 comb
+= update_svstate
.eq(1)
586 m
.next
= "ISSUE_START"
588 # returning to Execute? then, first update SRCSTEP
590 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
591 comb
+= new_svstate
.dststep
.eq(next_dststep
)
592 comb
+= update_svstate
.eq(1)
596 comb
+= core
.core_stopped_i
.eq(1)
597 comb
+= dbg
.core_stopped_i
.eq(1)
598 # while stopped, allow updating the PC and SVSTATE
599 with m
.If(self
.pc_i
.ok
):
600 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
601 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
602 sync
+= pc_changed
.eq(1)
603 with m
.If(self
.svstate_i
.ok
):
604 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
605 comb
+= update_svstate
.eq(1)
606 sync
+= sv_changed
.eq(1)
608 # need to decode the instruction again, after updating SRCSTEP
609 # in the previous state.
610 # mostly a copy of INSN_WAIT, but without the actual wait
611 with m
.State("DECODE_SV"):
612 # decode the instruction
613 sync
+= core
.e
.eq(pdecode2
.e
)
614 sync
+= core
.state
.eq(cur_state
)
615 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
616 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
617 m
.next
= "INSN_EXECUTE" # move to "execute"
619 # check if svstate needs updating: if so, write it to State Regfile
620 with m
.If(update_svstate
):
621 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
622 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
623 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
625 def execute_fsm(self
, m
, core
, pc_changed
, sv_changed
,
626 exec_insn_valid_i
, exec_insn_ready_o
,
627 exec_pc_valid_o
, exec_pc_ready_i
):
630 execute FSM. this interacts with the "issue" FSM
631 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
632 (outgoing). SVP64 RM prefixes have already been set up by the
633 "issue" phase, so execute is fairly straightforward.
638 pdecode2
= self
.pdecode2
641 core_busy_o
= core
.busy_o
# core is busy
642 core_ivalid_i
= core
.ivalid_i
# instruction is valid
643 core_issue_i
= core
.issue_i
# instruction is issued
644 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
646 with m
.FSM(name
="exec_fsm"):
648 # waiting for instruction bus (stays there until not busy)
649 with m
.State("INSN_START"):
650 comb
+= exec_insn_ready_o
.eq(1)
651 with m
.If(exec_insn_valid_i
):
652 comb
+= core_ivalid_i
.eq(1) # instruction is valid
653 comb
+= core_issue_i
.eq(1) # and issued
654 sync
+= sv_changed
.eq(0)
655 sync
+= pc_changed
.eq(0)
656 m
.next
= "INSN_ACTIVE" # move to "wait completion"
658 # instruction started: must wait till it finishes
659 with m
.State("INSN_ACTIVE"):
660 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
661 comb
+= core_ivalid_i
.eq(1) # instruction is valid
662 # note changes to PC and SVSTATE
663 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.SVSTATE
)):
664 sync
+= sv_changed
.eq(1)
665 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
666 sync
+= pc_changed
.eq(1)
667 with m
.If(~core_busy_o
): # instruction done!
668 comb
+= exec_pc_valid_o
.eq(1)
669 with m
.If(exec_pc_ready_i
):
670 comb
+= self
.insn_done
.eq(1)
671 m
.next
= "INSN_START" # back to fetch
673 def setup_peripherals(self
, m
):
674 comb
, sync
= m
.d
.comb
, m
.d
.sync
676 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
677 m
.submodules
.imem
= imem
= self
.imem
678 m
.submodules
.dbg
= dbg
= self
.dbg
680 m
.submodules
.jtag
= jtag
= self
.jtag
681 # TODO: UART2GDB mux, here, from external pin
682 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
683 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
685 cur_state
= self
.cur_state
687 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
689 for i
, sram
in enumerate(self
.sram4k
):
690 m
.submodules
["sram4k_%d" % i
] = sram
691 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
693 # XICS interrupt handler
695 m
.submodules
.xics_icp
= icp
= self
.xics_icp
696 m
.submodules
.xics_ics
= ics
= self
.xics_ics
697 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
698 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
700 # GPIO test peripheral
702 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
704 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
705 # XXX causes litex ECP5 test to get wrong idea about input and output
706 # (but works with verilator sim *sigh*)
707 #if self.gpio and self.xics:
708 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
710 # instruction decoder
711 pdecode
= create_pdecode()
712 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
714 m
.submodules
.svp64
= svp64
= self
.svp64
717 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
718 intrf
= self
.core
.regs
.rf
['int']
720 # clock delay power-on reset
721 cd_por
= ClockDomain(reset_less
=True)
722 cd_sync
= ClockDomain()
723 core_sync
= ClockDomain("coresync")
724 m
.domains
+= cd_por
, cd_sync
, core_sync
726 ti_rst
= Signal(reset_less
=True)
727 delay
= Signal(range(4), reset
=3)
728 with m
.If(delay
!= 0):
729 m
.d
.por
+= delay
.eq(delay
- 1)
730 comb
+= cd_por
.clk
.eq(ClockSignal())
732 # power-on reset delay
733 core_rst
= ResetSignal("coresync")
734 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
735 comb
+= core_rst
.eq(ti_rst
)
737 # busy/halted signals from core
738 comb
+= self
.busy_o
.eq(core
.busy_o
)
739 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
741 # temporary hack: says "go" immediately for both address gen and ST
743 ldst
= core
.fus
.fus
['ldst0']
744 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
745 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
746 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
750 def elaborate(self
, platform
):
753 comb
, sync
= m
.d
.comb
, m
.d
.sync
754 cur_state
= self
.cur_state
755 pdecode2
= self
.pdecode2
759 # set up peripherals and core
760 core_rst
= self
.setup_peripherals(m
)
762 # PC and instruction from I-Memory
763 comb
+= self
.pc_o
.eq(cur_state
.pc
)
764 pc_changed
= Signal() # note write to PC
765 sv_changed
= Signal() # note write to SVSTATE
767 # read state either from incoming override or from regfile
768 # TODO: really should be doing MSR in the same way
769 pc
= state_get(m
, self
.pc_i
, "pc", # read PC
770 self
.state_r_pc
, StateRegs
.PC
)
771 svstate
= state_get(m
, self
.svstate_i
, "svstate", # read SVSTATE
772 self
.state_r_sv
, StateRegs
.SVSTATE
)
774 # don't write pc every cycle
775 comb
+= self
.state_w_pc
.wen
.eq(0)
776 comb
+= self
.state_w_pc
.data_i
.eq(0)
778 # don't read msr every cycle
779 comb
+= self
.state_r_msr
.ren
.eq(0)
781 # address of the next instruction, in the absence of a branch
782 # depends on the instruction size
783 nia
= Signal(64, reset_less
=True)
785 # connect up debug signals
786 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
787 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
788 comb
+= dbg
.state
.pc
.eq(pc
)
789 comb
+= dbg
.state
.svstate
.eq(svstate
)
790 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
792 # pass the prefix mode from Fetch to Issue, so the latter can loop
794 is_svp64_mode
= Signal()
796 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
797 # these are the handshake signals between fetch and decode/execute
799 # fetch FSM can run as soon as the PC is valid
800 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
801 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
803 # fetch FSM hands over the instruction to be decoded / issued
804 fetch_insn_valid_o
= Signal()
805 fetch_insn_ready_i
= Signal()
807 # predicate fetch FSM decodes and fetches the predicate
808 pred_insn_valid_i
= Signal()
809 pred_insn_ready_o
= Signal()
811 # predicate fetch FSM delivers the masks
812 pred_mask_valid_o
= Signal()
813 pred_mask_ready_i
= Signal()
815 # issue FSM delivers the instruction to the be executed
816 exec_insn_valid_i
= Signal()
817 exec_insn_ready_o
= Signal()
819 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
820 exec_pc_valid_o
= Signal()
821 exec_pc_ready_i
= Signal()
823 # the FSMs here are perhaps unusual in that they detect conditions
824 # then "hold" information, combinatorially, for the core
825 # (as opposed to using sync - which would be on a clock's delay)
826 # this includes the actual opcode, valid flags and so on.
828 # Fetch, then predicate fetch, then Issue, then Execute.
829 # Issue is where the VL for-loop # lives. the ready/valid
830 # signalling is used to communicate between the four.
832 self
.fetch_fsm(m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
833 fetch_pc_ready_o
, fetch_pc_valid_i
,
834 fetch_insn_valid_o
, fetch_insn_ready_i
)
836 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
837 dbg
, core_rst
, is_svp64_mode
,
838 fetch_pc_ready_o
, fetch_pc_valid_i
,
839 fetch_insn_valid_o
, fetch_insn_ready_i
,
840 pred_insn_valid_i
, pred_insn_ready_o
,
841 pred_mask_valid_o
, pred_mask_ready_i
,
842 exec_insn_valid_i
, exec_insn_ready_o
,
843 exec_pc_valid_o
, exec_pc_ready_i
)
845 self
.fetch_predicate_fsm(m
,
846 pred_insn_valid_i
, pred_insn_ready_o
,
847 pred_mask_valid_o
, pred_mask_ready_i
)
849 self
.execute_fsm(m
, core
, pc_changed
, sv_changed
,
850 exec_insn_valid_i
, exec_insn_ready_o
,
851 exec_pc_valid_o
, exec_pc_ready_i
)
853 # this bit doesn't have to be in the FSM: connect up to read
854 # regfiles on demand from DMI
857 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
858 # (which uses that in PowerDecoder2 to raise 0x900 exception)
859 self
.tb_dec_fsm(m
, cur_state
.dec
)
863 def do_dmi(self
, m
, dbg
):
864 """deals with DMI debug requests
866 currently only provides read requests for the INT regfile, CR and XER
867 it will later also deal with *writing* to these regfiles.
871 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
872 intrf
= self
.core
.regs
.rf
['int']
874 with m
.If(d_reg
.req
): # request for regfile access being made
875 # TODO: error-check this
876 # XXX should this be combinatorial? sync better?
878 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
880 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
881 comb
+= self
.int_r
.ren
.eq(1)
882 d_reg_delay
= Signal()
883 sync
+= d_reg_delay
.eq(d_reg
.req
)
884 with m
.If(d_reg_delay
):
885 # data arrives one clock later
886 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
887 comb
+= d_reg
.ack
.eq(1)
889 # sigh same thing for CR debug
890 with m
.If(d_cr
.req
): # request for regfile access being made
891 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
892 d_cr_delay
= Signal()
893 sync
+= d_cr_delay
.eq(d_cr
.req
)
894 with m
.If(d_cr_delay
):
895 # data arrives one clock later
896 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
897 comb
+= d_cr
.ack
.eq(1)
900 with m
.If(d_xer
.req
): # request for regfile access being made
901 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
902 d_xer_delay
= Signal()
903 sync
+= d_xer_delay
.eq(d_xer
.req
)
904 with m
.If(d_xer_delay
):
905 # data arrives one clock later
906 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
907 comb
+= d_xer
.ack
.eq(1)
909 def tb_dec_fsm(self
, m
, spr_dec
):
912 this is a FSM for updating either dec or tb. it runs alternately
913 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
914 value to DEC, however the regfile has "passthrough" on it so this
917 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
920 comb
, sync
= m
.d
.comb
, m
.d
.sync
921 fast_rf
= self
.core
.regs
.rf
['fast']
922 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
923 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
927 # initiates read of current DEC
928 with m
.State("DEC_READ"):
929 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
930 comb
+= fast_r_dectb
.ren
.eq(1)
933 # waits for DEC read to arrive (1 cycle), updates with new value
934 with m
.State("DEC_WRITE"):
936 # TODO: MSR.LPCR 32-bit decrement mode
937 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
938 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
939 comb
+= fast_w_dectb
.wen
.eq(1)
940 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
941 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
944 # initiates read of current TB
945 with m
.State("TB_READ"):
946 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
947 comb
+= fast_r_dectb
.ren
.eq(1)
950 # waits for read TB to arrive, initiates write of current TB
951 with m
.State("TB_WRITE"):
953 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
954 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
955 comb
+= fast_w_dectb
.wen
.eq(1)
956 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
962 yield from self
.pc_i
.ports()
965 yield from self
.core
.ports()
966 yield from self
.imem
.ports()
967 yield self
.core_bigendian_i
973 def external_ports(self
):
974 ports
= self
.pc_i
.ports()
975 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
979 ports
+= list(self
.jtag
.external_ports())
981 # don't add DMI if JTAG is enabled
982 ports
+= list(self
.dbg
.dmi
.ports())
984 ports
+= list(self
.imem
.ibus
.fields
.values())
985 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
988 for sram
in self
.sram4k
:
989 ports
+= list(sram
.bus
.fields
.values())
992 ports
+= list(self
.xics_icp
.bus
.fields
.values())
993 ports
+= list(self
.xics_ics
.bus
.fields
.values())
994 ports
.append(self
.int_level_i
)
997 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
998 ports
.append(self
.gpio_o
)
1006 class TestIssuer(Elaboratable
):
1007 def __init__(self
, pspec
):
1008 self
.ti
= TestIssuerInternal(pspec
)
1010 self
.pll
= DummyPLL()
1012 # PLL direct clock or not
1013 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1015 self
.pll_18_o
= Signal(reset_less
=True)
1017 def elaborate(self
, platform
):
1021 # TestIssuer runs at direct clock
1022 m
.submodules
.ti
= ti
= self
.ti
1023 cd_int
= ClockDomain("coresync")
1026 # ClockSelect runs at PLL output internal clock rate
1027 m
.submodules
.pll
= pll
= self
.pll
1029 # add clock domains from PLL
1030 cd_pll
= ClockDomain("pllclk")
1033 # PLL clock established. has the side-effect of running clklsel
1034 # at the PLL's speed (see DomainRenamer("pllclk") above)
1035 pllclk
= ClockSignal("pllclk")
1036 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1038 # wire up external 24mhz to PLL
1039 comb
+= pll
.clk_24_i
.eq(ClockSignal())
1041 # output 18 mhz PLL test signal
1042 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
1044 # now wire up ResetSignals. don't mind them being in this domain
1045 pll_rst
= ResetSignal("pllclk")
1046 comb
+= pll_rst
.eq(ResetSignal())
1048 # internal clock is set to selector clock-out. has the side-effect of
1049 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1050 intclk
= ClockSignal("coresync")
1052 comb
+= intclk
.eq(pll
.clk_pll_o
)
1054 comb
+= intclk
.eq(ClockSignal())
1059 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1060 [ClockSignal(), ResetSignal()]
1062 def external_ports(self
):
1063 ports
= self
.ti
.external_ports()
1064 ports
.append(ClockSignal())
1065 ports
.append(ResetSignal())
1067 ports
.append(self
.pll
.clk_sel_i
)
1068 ports
.append(self
.pll_18_o
)
1069 ports
.append(self
.pll
.pll_lck_o
)
1073 if __name__
== '__main__':
1074 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1080 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1081 imem_ifacetype
='bare_wb',
1086 dut
= TestIssuer(pspec
)
1087 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1089 if len(sys
.argv
) == 1:
1090 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1091 with
open("test_issuer.il", "w") as f
: