3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
41 from soc
.clock
.select
import ClockSelect
42 from soc
.clock
.dummypll
import DummyPLL
43 from soc
.sv
.svstate
import SVSTATERec
46 from nmutil
.util
import rising_edge
48 def get_insn(f_instr_o
, pc
):
49 if f_instr_o
.width
== 32:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o
.word_select(pc
[2], 32)
55 # gets state input or reads from state regfile
56 def state_get(m
, state_i
, name
, regfile
, regnum
):
60 res
= Signal(64, reset_less
=True, name
=name
)
61 res_ok_delay
= Signal(name
="%s_ok_delay" % name
)
62 sync
+= res_ok_delay
.eq(~state_i
.ok
)
63 with m
.If(state_i
.ok
):
64 # incoming override (start from pc_i)
65 comb
+= res
.eq(state_i
.data
)
67 # otherwise read StateRegs regfile for PC...
68 comb
+= regfile
.ren
.eq(1<<regnum
)
69 # ... but on a 1-clock delay
70 with m
.If(res_ok_delay
):
71 comb
+= res
.eq(regfile
.data_o
)
74 def get_predint(m
, mask
):
75 """decode SVP64 predicate integer mask field to reg number and invert
76 this is identical to the equivalent function in ISACaller except that
77 it doesn't read the INT directly, it just decodes "what needs to be done"
78 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
84 with m
.Case(SVP64PredInt
.ALWAYS
.value
):
87 with m
.Case(SVP64PredInt
.R3_UNARY
.value
):
90 with m
.Case(SVP64PredInt
.R3
.value
):
92 with m
.Case(SVP64PredInt
.R3_N
.value
):
95 with m
.Case(SVP64PredInt
.R10
.value
):
96 comb
+= regread
.eq(10)
97 with m
.Case(SVP64PredInt
.R10_N
.value
):
98 comb
+= regread
.eq(10)
100 with m
.Case(SVP64PredInt
.R30
.value
):
101 comb
+= regread
.eq(30)
102 with m
.Case(SVP64PredInt
.R30_N
.value
):
103 comb
+= regread
.eq(30)
105 return regread
, invert
, unary
107 def get_predcr(m
, mask
):
108 """decode SVP64 predicate CR to reg number field and invert status
109 this is identical to _get_predcr in ISACaller
114 with m
.Case(SVP64PredCR
.LT
.value
):
117 with m
.Case(SVP64PredCR
.GE
.value
):
120 with m
.Case(SVP64PredCR
.GT
.value
):
123 with m
.Case(SVP64PredCR
.LE
.value
):
126 with m
.Case(SVP64PredCR
.EQ
.value
):
129 with m
.Case(SVP64PredCR
.NE
.value
):
132 with m
.Case(SVP64PredCR
.SO
.value
):
135 with m
.Case(SVP64PredCR
.NS
.value
):
141 class TestIssuerInternal(Elaboratable
):
142 """TestIssuer - reads instructions from TestMemory and issues them
144 efficiency and speed is not the main goal here: functional correctness
145 and code clarity is. optimisations (which almost 100% interfere with
146 easy understanding) come later.
148 def __init__(self
, pspec
):
150 # test is SVP64 is to be enabled
151 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
153 # JTAG interface. add this right at the start because if it's
154 # added it *modifies* the pspec, by adding enable/disable signals
155 # for parts of the rest of the core
156 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
158 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
160 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
161 # add signals to pspec to enable/disable icache and dcache
162 # (or data and intstruction wishbone if icache/dcache not included)
163 # https://bugs.libre-soc.org/show_bug.cgi?id=520
164 # TODO: do we actually care if these are not domain-synchronised?
165 # honestly probably not.
166 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
167 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
168 self
.wb_sram_en
= self
.jtag
.wb_sram_en
170 self
.wb_sram_en
= Const(1)
172 # add 4k sram blocks?
173 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
174 pspec
.sram4x4kblock
== True)
178 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
181 # add interrupt controller?
182 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
184 self
.xics_icp
= XICS_ICP()
185 self
.xics_ics
= XICS_ICS()
186 self
.int_level_i
= self
.xics_ics
.int_level_i
188 # add GPIO peripheral?
189 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
191 self
.simple_gpio
= SimpleGPIO()
192 self
.gpio_o
= self
.simple_gpio
.gpio_o
194 # main instruction core. suitable for prototyping / demo only
195 self
.core
= core
= NonProductionCore(pspec
)
197 # instruction decoder. goes into Trap Record
198 pdecode
= create_pdecode()
199 self
.cur_state
= CoreState("cur") # current state (MSR/PC/SVSTATE)
200 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
201 opkls
=IssuerDecode2ToOperand
,
202 svp64_en
=self
.svp64_en
)
204 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
206 # Test Instruction memory
207 self
.imem
= ConfigFetchUnit(pspec
).fu
210 self
.dbg
= CoreDebug()
212 # instruction go/monitor
213 self
.pc_o
= Signal(64, reset_less
=True)
214 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
215 self
.svstate_i
= Data(32, "svstate_i") # ditto
216 self
.core_bigendian_i
= Signal() # TODO: set based on MSR.LE
217 self
.busy_o
= Signal(reset_less
=True)
218 self
.memerr_o
= Signal(reset_less
=True)
220 # STATE regfile read /write ports for PC, MSR, SVSTATE
221 staterf
= self
.core
.regs
.rf
['state']
222 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
223 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
224 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
225 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
226 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
228 # DMI interface access
229 intrf
= self
.core
.regs
.rf
['int']
230 crrf
= self
.core
.regs
.rf
['cr']
231 xerrf
= self
.core
.regs
.rf
['xer']
232 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
233 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
234 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
237 self
.int_pred
= intrf
.r_ports
['pred'] # INT predicate read
238 self
.cr_pred
= crrf
.r_ports
['cr_pred'] # CR predicate read
240 # hack method of keeping an eye on whether branch/trap set the PC
241 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
242 self
.state_nia
.wen
.name
= 'state_nia_wen'
244 # pulse to synchronize the simulator at instruction end
245 self
.insn_done
= Signal()
248 # store copies of predicate masks
249 self
.srcmask
= Signal(64)
250 self
.dstmask
= Signal(64)
252 def fetch_fsm(self
, m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
253 fetch_pc_ready_o
, fetch_pc_valid_i
,
254 fetch_insn_valid_o
, fetch_insn_ready_i
):
257 this FSM performs fetch of raw instruction data, partial-decodes
258 it 32-bit at a time to detect SVP64 prefixes, and will optionally
259 read a 2nd 32-bit quantity if that occurs.
263 pdecode2
= self
.pdecode2
264 cur_state
= self
.cur_state
265 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
267 msr_read
= Signal(reset
=1)
269 with m
.FSM(name
='fetch_fsm'):
272 with m
.State("IDLE"):
273 comb
+= fetch_pc_ready_o
.eq(1)
274 with m
.If(fetch_pc_valid_i
):
275 # instruction allowed to go: start by reading the PC
276 # capture the PC and also drop it into Insn Memory
277 # we have joined a pair of combinatorial memory
278 # lookups together. this is Generally Bad.
279 comb
+= self
.imem
.a_pc_i
.eq(pc
)
280 comb
+= self
.imem
.a_valid_i
.eq(1)
281 comb
+= self
.imem
.f_valid_i
.eq(1)
282 sync
+= cur_state
.pc
.eq(pc
)
283 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
285 # initiate read of MSR. arrives one clock later
286 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
287 sync
+= msr_read
.eq(0)
289 m
.next
= "INSN_READ" # move to "wait for bus" phase
291 # dummy pause to find out why simulation is not keeping up
292 with m
.State("INSN_READ"):
293 # one cycle later, msr/sv read arrives. valid only once.
294 with m
.If(~msr_read
):
295 sync
+= msr_read
.eq(1) # yeah don't read it again
296 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
297 with m
.If(self
.imem
.f_busy_o
): # zzz...
298 # busy: stay in wait-read
299 comb
+= self
.imem
.a_valid_i
.eq(1)
300 comb
+= self
.imem
.f_valid_i
.eq(1)
302 # not busy: instruction fetched
303 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
306 # decode the SVP64 prefix, if any
307 comb
+= svp64
.raw_opcode_in
.eq(insn
)
308 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
309 # pass the decoded prefix (if any) to PowerDecoder2
310 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
311 # remember whether this is a prefixed instruction, so
312 # the FSM can readily loop when VL==0
313 sync
+= is_svp64_mode
.eq(svp64
.is_svp64_mode
)
314 # calculate the address of the following instruction
315 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
316 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
317 with m
.If(~svp64
.is_svp64_mode
):
318 # with no prefix, store the instruction
319 # and hand it directly to the next FSM
320 sync
+= dec_opcode_i
.eq(insn
)
321 m
.next
= "INSN_READY"
323 # fetch the rest of the instruction from memory
324 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
325 comb
+= self
.imem
.a_valid_i
.eq(1)
326 comb
+= self
.imem
.f_valid_i
.eq(1)
327 m
.next
= "INSN_READ2"
329 # not SVP64 - 32-bit only
330 sync
+= nia
.eq(cur_state
.pc
+ 4)
331 sync
+= dec_opcode_i
.eq(insn
)
332 m
.next
= "INSN_READY"
334 with m
.State("INSN_READ2"):
335 with m
.If(self
.imem
.f_busy_o
): # zzz...
336 # busy: stay in wait-read
337 comb
+= self
.imem
.a_valid_i
.eq(1)
338 comb
+= self
.imem
.f_valid_i
.eq(1)
340 # not busy: instruction fetched
341 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
342 sync
+= dec_opcode_i
.eq(insn
)
343 m
.next
= "INSN_READY"
344 # TODO: probably can start looking at pdecode2.rm_dec
345 # here or maybe even in INSN_READ state, if svp64_mode
346 # detected, in order to trigger - and wait for - the
348 pmode
= pdecode2
.rm_dec
.predmode
350 if pmode != SVP64PredMode.ALWAYS.value:
351 fire predicate loading FSM and wait before
354 sync += self.srcmask.eq(-1) # set to all 1s
355 sync += self.dstmask.eq(-1) # set to all 1s
356 m.next = "INSN_READY"
359 with m
.State("INSN_READY"):
360 # hand over the instruction, to be decoded
361 comb
+= fetch_insn_valid_o
.eq(1)
362 with m
.If(fetch_insn_ready_i
):
365 def fetch_predicate_fsm(self
, m
,
366 pred_insn_valid_i
, pred_insn_ready_o
,
367 pred_mask_valid_o
, pred_mask_ready_i
):
368 """fetch_predicate_fsm - obtains (constructs in the case of CR)
369 src/dest predicate masks
371 https://bugs.libre-soc.org/show_bug.cgi?id=617
372 the predicates can be read here, by using IntRegs r_ports['pred']
373 or CRRegs r_ports['pred']. in the case of CRs it will have to
374 be done through multiple reads, extracting one relevant at a time.
375 later, a faster way would be to use the 32-bit-wide CR port but
376 this is more complex decoding, here. equivalent code used in
377 ISACaller is "from soc.decoder.isa.caller import get_predcr"
381 pdecode2
= self
.pdecode2
382 rm_dec
= pdecode2
.rm_dec
# SVP64RMModeDecode
383 predmode
= rm_dec
.predmode
384 srcpred
, dstpred
= rm_dec
.srcpred
, rm_dec
.dstpred
385 cr_pred
, int_pred
= self
.cr_pred
, self
.int_pred
# read regfiles
386 # if predmode == INT:
387 # INT-src sregread, sinvert, sunary = get_predint(m, srcpred)
388 # INT-dst dregread, dinvert, dunary = get_predint(m, dstpred)
389 # TODO read INT-src and INT-dst into self.srcmask+dstmask
390 # elif predmode == CR:
391 # CR-src sidx, sinvert = get_predcr(m, srcpred)
392 # CR-dst didx, dinvert = get_predcr(m, dstpred)
393 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
394 # for cr_idx = FSM-state-loop(0..VL-1):
395 # FSM-state-trigger-CR-read:
396 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
397 # comb += cr_pred.ren.eq(cr_ren)
398 # FSM-state-1-clock-later-actual-Read:
399 # cr_field = Signal(4)
401 # # read the CR field, select the appropriate bit
402 # comb += cr_field.eq(cr_pred.data_o)
403 # comb += cr_bit.eq(cr_field.bit_select(idx)))
404 # # just like in branch BO tests
405 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
407 # sync += self.srcmask.eq(-1) # set to all 1s
408 # sync += self.dstmask.eq(-1) # set to all 1s
409 with m
.FSM(name
="fetch_predicate"):
411 with m
.State("FETCH_PRED_IDLE"):
412 comb
+= pred_insn_ready_o
.eq(1)
413 with m
.If(pred_insn_valid_i
):
414 sync
+= self
.srcmask
.eq(-1)
415 sync
+= self
.dstmask
.eq(-1)
416 m
.next
= "FETCH_PRED_DONE"
418 with m
.State("FETCH_PRED_DONE"):
419 comb
+= pred_mask_valid_o
.eq(1)
420 with m
.If(pred_mask_ready_i
):
421 m
.next
= "FETCH_PRED_IDLE"
423 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
424 dbg
, core_rst
, is_svp64_mode
,
425 fetch_pc_ready_o
, fetch_pc_valid_i
,
426 fetch_insn_valid_o
, fetch_insn_ready_i
,
427 pred_insn_valid_i
, pred_insn_ready_o
,
428 pred_mask_valid_o
, pred_mask_ready_i
,
429 exec_insn_valid_i
, exec_insn_ready_o
,
430 exec_pc_valid_o
, exec_pc_ready_i
):
433 decode / issue FSM. this interacts with the "fetch" FSM
434 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
435 (outgoing). also interacts with the "execute" FSM
436 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
438 SVP64 RM prefixes have already been set up by the
439 "fetch" phase, so execute is fairly straightforward.
444 pdecode2
= self
.pdecode2
445 cur_state
= self
.cur_state
448 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
450 # for updating svstate (things like srcstep etc.)
451 update_svstate
= Signal() # set this (below) if updating
452 new_svstate
= SVSTATERec("new_svstate")
453 comb
+= new_svstate
.eq(cur_state
.svstate
)
455 # precalculate srcstep+1 and dststep+1
456 cur_srcstep
= cur_state
.svstate
.srcstep
457 cur_dststep
= cur_state
.svstate
.dststep
458 next_srcstep
= Signal
.like(cur_srcstep
)
459 next_dststep
= Signal
.like(cur_dststep
)
460 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
461 comb
+= next_dststep
.eq(cur_state
.svstate
.dststep
+1)
463 with m
.FSM(name
="issue_fsm"):
465 # sync with the "fetch" phase which is reading the instruction
466 # at this point, there is no instruction running, that
467 # could inadvertently update the PC.
468 with m
.State("ISSUE_START"):
469 # wait on "core stop" release, before next fetch
470 # need to do this here, in case we are in a VL==0 loop
471 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
472 comb
+= fetch_pc_valid_i
.eq(1) # tell fetch to start
473 with m
.If(fetch_pc_ready_o
): # fetch acknowledged us
476 # tell core it's stopped, and acknowledge debug handshake
477 comb
+= core
.core_stopped_i
.eq(1)
478 comb
+= dbg
.core_stopped_i
.eq(1)
479 # while stopped, allow updating the PC and SVSTATE
480 with m
.If(self
.pc_i
.ok
):
481 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
482 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
483 sync
+= pc_changed
.eq(1)
484 with m
.If(self
.svstate_i
.ok
):
485 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
486 comb
+= update_svstate
.eq(1)
487 sync
+= sv_changed
.eq(1)
489 # decode the instruction when it arrives
490 with m
.State("INSN_WAIT"):
491 comb
+= fetch_insn_ready_i
.eq(1)
492 with m
.If(fetch_insn_valid_o
):
493 # decode the instruction
494 sync
+= core
.e
.eq(pdecode2
.e
)
495 sync
+= core
.state
.eq(cur_state
)
496 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
497 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
498 # set RA_OR_ZERO detection in satellite decoders
499 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
500 # loop into ISSUE_START if it's a SVP64 instruction
501 # and VL == 0. this because VL==0 is a for-loop
502 # from 0 to 0 i.e. always, always a NOP.
503 cur_vl
= cur_state
.svstate
.vl
504 with m
.If(is_svp64_mode
& (cur_vl
== 0)):
505 # update the PC before fetching the next instruction
506 # since we are in a VL==0 loop, no instruction was
507 # executed that we could be overwriting
508 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
509 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
510 comb
+= self
.insn_done
.eq(1)
511 m
.next
= "ISSUE_START"
513 m
.next
= "PRED_START" # start fetching the predicate
515 with m
.State("PRED_START"):
516 comb
+= pred_insn_valid_i
.eq(1) # tell fetch_pred to start
517 with m
.If(pred_insn_ready_o
): # fetch_pred acknowledged us
520 with m
.State("MASK_WAIT"):
521 comb
+= pred_mask_ready_i
.eq(1) # ready to receive the masks
522 with m
.If(pred_mask_valid_o
): # predication masks are ready
523 m
.next
= "INSN_EXECUTE"
525 # handshake with execution FSM, move to "wait" once acknowledged
526 with m
.State("INSN_EXECUTE"):
527 # with m.If(is_svp64_mode):
528 # TODO advance src/dst step to "skip" over predicated-out
529 # from self.srcmask and self.dstmask
530 # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
531 # but still without exceeding VL in either case
532 # IMPORTANT: when changing src/dest step, have to
533 # jump to m.next = "DECODE_SV" to deal with the change in
536 with m
.If(is_svp64_mode
):
538 pred_src_zero
= pdecode2
.rm_dec
.pred_sz
539 pred_dst_zero
= pdecode2
.rm_dec
.pred_dz
542 if not pred_src_zero:
543 if (((1<<cur_srcstep) & self.srcmask) == 0) and
545 comb += update_svstate.eq(1)
546 comb += new_svstate.srcstep.eq(next_srcstep)
547 sync += sv_changed.eq(1)
549 if not pred_dst_zero:
550 if (((1<<cur_dststep) & self.dstmask) == 0) and
552 comb += new_svstate.dststep.eq(next_dststep)
553 comb += update_svstate.eq(1)
554 sync += sv_changed.eq(1)
560 comb
+= exec_insn_valid_i
.eq(1) # trigger execute
561 with m
.If(exec_insn_ready_o
): # execute acknowledged us
562 m
.next
= "EXECUTE_WAIT"
564 with m
.State("EXECUTE_WAIT"):
565 # wait on "core stop" release, at instruction end
566 # need to do this here, in case we are in a VL>1 loop
567 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
568 comb
+= exec_pc_ready_i
.eq(1)
569 with m
.If(exec_pc_valid_o
):
571 # was this the last loop iteration?
573 cur_vl
= cur_state
.svstate
.vl
574 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
576 # if either PC or SVSTATE were changed by the previous
577 # instruction, go directly back to Fetch, without
578 # updating either PC or SVSTATE
579 with m
.If(pc_changed | sv_changed
):
580 m
.next
= "ISSUE_START"
582 # also return to Fetch, when no output was a vector
583 # (regardless of SRCSTEP and VL), or when the last
584 # instruction was really the last one of the VL loop
585 with m
.Elif((~pdecode2
.loop_continue
) | is_last
):
586 # before going back to fetch, update the PC state
587 # register with the NIA.
588 # ok here we are not reading the branch unit.
589 # TODO: this just blithely overwrites whatever
590 # pipeline updated the PC
591 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
592 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
593 # reset SRCSTEP before returning to Fetch
594 with m
.If(pdecode2
.loop_continue
):
595 comb
+= new_svstate
.srcstep
.eq(0)
596 comb
+= new_svstate
.dststep
.eq(0)
597 comb
+= update_svstate
.eq(1)
598 m
.next
= "ISSUE_START"
600 # returning to Execute? then, first update SRCSTEP
602 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
603 comb
+= new_svstate
.dststep
.eq(next_dststep
)
604 comb
+= update_svstate
.eq(1)
608 comb
+= core
.core_stopped_i
.eq(1)
609 comb
+= dbg
.core_stopped_i
.eq(1)
610 # while stopped, allow updating the PC and SVSTATE
611 with m
.If(self
.pc_i
.ok
):
612 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
613 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
614 sync
+= pc_changed
.eq(1)
615 with m
.If(self
.svstate_i
.ok
):
616 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
617 comb
+= update_svstate
.eq(1)
618 sync
+= sv_changed
.eq(1)
620 # need to decode the instruction again, after updating SRCSTEP
621 # in the previous state.
622 # mostly a copy of INSN_WAIT, but without the actual wait
623 with m
.State("DECODE_SV"):
624 # decode the instruction
625 sync
+= core
.e
.eq(pdecode2
.e
)
626 sync
+= core
.state
.eq(cur_state
)
627 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
628 sync
+= core
.sv_a_nz
.eq(pdecode2
.sv_a_nz
)
629 m
.next
= "INSN_EXECUTE" # move to "execute"
631 # check if svstate needs updating: if so, write it to State Regfile
632 with m
.If(update_svstate
):
633 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
634 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
635 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
637 def execute_fsm(self
, m
, core
, pc_changed
, sv_changed
,
638 exec_insn_valid_i
, exec_insn_ready_o
,
639 exec_pc_valid_o
, exec_pc_ready_i
):
642 execute FSM. this interacts with the "issue" FSM
643 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
644 (outgoing). SVP64 RM prefixes have already been set up by the
645 "issue" phase, so execute is fairly straightforward.
650 pdecode2
= self
.pdecode2
653 core_busy_o
= core
.busy_o
# core is busy
654 core_ivalid_i
= core
.ivalid_i
# instruction is valid
655 core_issue_i
= core
.issue_i
# instruction is issued
656 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
658 with m
.FSM(name
="exec_fsm"):
660 # waiting for instruction bus (stays there until not busy)
661 with m
.State("INSN_START"):
662 comb
+= exec_insn_ready_o
.eq(1)
663 with m
.If(exec_insn_valid_i
):
664 comb
+= core_ivalid_i
.eq(1) # instruction is valid
665 comb
+= core_issue_i
.eq(1) # and issued
666 sync
+= sv_changed
.eq(0)
667 sync
+= pc_changed
.eq(0)
668 m
.next
= "INSN_ACTIVE" # move to "wait completion"
670 # instruction started: must wait till it finishes
671 with m
.State("INSN_ACTIVE"):
672 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
673 comb
+= core_ivalid_i
.eq(1) # instruction is valid
674 # note changes to PC and SVSTATE
675 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.SVSTATE
)):
676 sync
+= sv_changed
.eq(1)
677 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
678 sync
+= pc_changed
.eq(1)
679 with m
.If(~core_busy_o
): # instruction done!
680 comb
+= exec_pc_valid_o
.eq(1)
681 with m
.If(exec_pc_ready_i
):
682 comb
+= self
.insn_done
.eq(1)
683 m
.next
= "INSN_START" # back to fetch
685 def setup_peripherals(self
, m
):
686 comb
, sync
= m
.d
.comb
, m
.d
.sync
688 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
689 m
.submodules
.imem
= imem
= self
.imem
690 m
.submodules
.dbg
= dbg
= self
.dbg
692 m
.submodules
.jtag
= jtag
= self
.jtag
693 # TODO: UART2GDB mux, here, from external pin
694 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
695 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
697 cur_state
= self
.cur_state
699 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
701 for i
, sram
in enumerate(self
.sram4k
):
702 m
.submodules
["sram4k_%d" % i
] = sram
703 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
705 # XICS interrupt handler
707 m
.submodules
.xics_icp
= icp
= self
.xics_icp
708 m
.submodules
.xics_ics
= ics
= self
.xics_ics
709 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
710 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
712 # GPIO test peripheral
714 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
716 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
717 # XXX causes litex ECP5 test to get wrong idea about input and output
718 # (but works with verilator sim *sigh*)
719 #if self.gpio and self.xics:
720 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
722 # instruction decoder
723 pdecode
= create_pdecode()
724 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
726 m
.submodules
.svp64
= svp64
= self
.svp64
729 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
730 intrf
= self
.core
.regs
.rf
['int']
732 # clock delay power-on reset
733 cd_por
= ClockDomain(reset_less
=True)
734 cd_sync
= ClockDomain()
735 core_sync
= ClockDomain("coresync")
736 m
.domains
+= cd_por
, cd_sync
, core_sync
738 ti_rst
= Signal(reset_less
=True)
739 delay
= Signal(range(4), reset
=3)
740 with m
.If(delay
!= 0):
741 m
.d
.por
+= delay
.eq(delay
- 1)
742 comb
+= cd_por
.clk
.eq(ClockSignal())
744 # power-on reset delay
745 core_rst
= ResetSignal("coresync")
746 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
747 comb
+= core_rst
.eq(ti_rst
)
749 # busy/halted signals from core
750 comb
+= self
.busy_o
.eq(core
.busy_o
)
751 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
753 # temporary hack: says "go" immediately for both address gen and ST
755 ldst
= core
.fus
.fus
['ldst0']
756 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
757 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
758 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
762 def elaborate(self
, platform
):
765 comb
, sync
= m
.d
.comb
, m
.d
.sync
766 cur_state
= self
.cur_state
767 pdecode2
= self
.pdecode2
771 # set up peripherals and core
772 core_rst
= self
.setup_peripherals(m
)
774 # PC and instruction from I-Memory
775 comb
+= self
.pc_o
.eq(cur_state
.pc
)
776 pc_changed
= Signal() # note write to PC
777 sv_changed
= Signal() # note write to SVSTATE
779 # read state either from incoming override or from regfile
780 # TODO: really should be doing MSR in the same way
781 pc
= state_get(m
, self
.pc_i
, "pc", # read PC
782 self
.state_r_pc
, StateRegs
.PC
)
783 svstate
= state_get(m
, self
.svstate_i
, "svstate", # read SVSTATE
784 self
.state_r_sv
, StateRegs
.SVSTATE
)
786 # don't write pc every cycle
787 comb
+= self
.state_w_pc
.wen
.eq(0)
788 comb
+= self
.state_w_pc
.data_i
.eq(0)
790 # don't read msr every cycle
791 comb
+= self
.state_r_msr
.ren
.eq(0)
793 # address of the next instruction, in the absence of a branch
794 # depends on the instruction size
795 nia
= Signal(64, reset_less
=True)
797 # connect up debug signals
798 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
799 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
800 comb
+= dbg
.state
.pc
.eq(pc
)
801 comb
+= dbg
.state
.svstate
.eq(svstate
)
802 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
804 # pass the prefix mode from Fetch to Issue, so the latter can loop
806 is_svp64_mode
= Signal()
808 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
809 # these are the handshake signals between fetch and decode/execute
811 # fetch FSM can run as soon as the PC is valid
812 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
813 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
815 # fetch FSM hands over the instruction to be decoded / issued
816 fetch_insn_valid_o
= Signal()
817 fetch_insn_ready_i
= Signal()
819 # predicate fetch FSM decodes and fetches the predicate
820 pred_insn_valid_i
= Signal()
821 pred_insn_ready_o
= Signal()
823 # predicate fetch FSM delivers the masks
824 pred_mask_valid_o
= Signal()
825 pred_mask_ready_i
= Signal()
827 # issue FSM delivers the instruction to the be executed
828 exec_insn_valid_i
= Signal()
829 exec_insn_ready_o
= Signal()
831 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
832 exec_pc_valid_o
= Signal()
833 exec_pc_ready_i
= Signal()
835 # the FSMs here are perhaps unusual in that they detect conditions
836 # then "hold" information, combinatorially, for the core
837 # (as opposed to using sync - which would be on a clock's delay)
838 # this includes the actual opcode, valid flags and so on.
840 # Fetch, then predicate fetch, then Issue, then Execute.
841 # Issue is where the VL for-loop # lives. the ready/valid
842 # signalling is used to communicate between the four.
844 self
.fetch_fsm(m
, core
, pc
, svstate
, nia
, is_svp64_mode
,
845 fetch_pc_ready_o
, fetch_pc_valid_i
,
846 fetch_insn_valid_o
, fetch_insn_ready_i
)
848 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
849 dbg
, core_rst
, is_svp64_mode
,
850 fetch_pc_ready_o
, fetch_pc_valid_i
,
851 fetch_insn_valid_o
, fetch_insn_ready_i
,
852 pred_insn_valid_i
, pred_insn_ready_o
,
853 pred_mask_valid_o
, pred_mask_ready_i
,
854 exec_insn_valid_i
, exec_insn_ready_o
,
855 exec_pc_valid_o
, exec_pc_ready_i
)
857 self
.fetch_predicate_fsm(m
,
858 pred_insn_valid_i
, pred_insn_ready_o
,
859 pred_mask_valid_o
, pred_mask_ready_i
)
861 self
.execute_fsm(m
, core
, pc_changed
, sv_changed
,
862 exec_insn_valid_i
, exec_insn_ready_o
,
863 exec_pc_valid_o
, exec_pc_ready_i
)
865 # this bit doesn't have to be in the FSM: connect up to read
866 # regfiles on demand from DMI
869 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
870 # (which uses that in PowerDecoder2 to raise 0x900 exception)
871 self
.tb_dec_fsm(m
, cur_state
.dec
)
875 def do_dmi(self
, m
, dbg
):
876 """deals with DMI debug requests
878 currently only provides read requests for the INT regfile, CR and XER
879 it will later also deal with *writing* to these regfiles.
883 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
884 intrf
= self
.core
.regs
.rf
['int']
886 with m
.If(d_reg
.req
): # request for regfile access being made
887 # TODO: error-check this
888 # XXX should this be combinatorial? sync better?
890 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
892 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
893 comb
+= self
.int_r
.ren
.eq(1)
894 d_reg_delay
= Signal()
895 sync
+= d_reg_delay
.eq(d_reg
.req
)
896 with m
.If(d_reg_delay
):
897 # data arrives one clock later
898 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
899 comb
+= d_reg
.ack
.eq(1)
901 # sigh same thing for CR debug
902 with m
.If(d_cr
.req
): # request for regfile access being made
903 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
904 d_cr_delay
= Signal()
905 sync
+= d_cr_delay
.eq(d_cr
.req
)
906 with m
.If(d_cr_delay
):
907 # data arrives one clock later
908 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
909 comb
+= d_cr
.ack
.eq(1)
912 with m
.If(d_xer
.req
): # request for regfile access being made
913 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
914 d_xer_delay
= Signal()
915 sync
+= d_xer_delay
.eq(d_xer
.req
)
916 with m
.If(d_xer_delay
):
917 # data arrives one clock later
918 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
919 comb
+= d_xer
.ack
.eq(1)
921 def tb_dec_fsm(self
, m
, spr_dec
):
924 this is a FSM for updating either dec or tb. it runs alternately
925 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
926 value to DEC, however the regfile has "passthrough" on it so this
929 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
932 comb
, sync
= m
.d
.comb
, m
.d
.sync
933 fast_rf
= self
.core
.regs
.rf
['fast']
934 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
935 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
939 # initiates read of current DEC
940 with m
.State("DEC_READ"):
941 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
942 comb
+= fast_r_dectb
.ren
.eq(1)
945 # waits for DEC read to arrive (1 cycle), updates with new value
946 with m
.State("DEC_WRITE"):
948 # TODO: MSR.LPCR 32-bit decrement mode
949 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
950 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
951 comb
+= fast_w_dectb
.wen
.eq(1)
952 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
953 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
956 # initiates read of current TB
957 with m
.State("TB_READ"):
958 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
959 comb
+= fast_r_dectb
.ren
.eq(1)
962 # waits for read TB to arrive, initiates write of current TB
963 with m
.State("TB_WRITE"):
965 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
966 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
967 comb
+= fast_w_dectb
.wen
.eq(1)
968 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
974 yield from self
.pc_i
.ports()
977 yield from self
.core
.ports()
978 yield from self
.imem
.ports()
979 yield self
.core_bigendian_i
985 def external_ports(self
):
986 ports
= self
.pc_i
.ports()
987 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
991 ports
+= list(self
.jtag
.external_ports())
993 # don't add DMI if JTAG is enabled
994 ports
+= list(self
.dbg
.dmi
.ports())
996 ports
+= list(self
.imem
.ibus
.fields
.values())
997 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
1000 for sram
in self
.sram4k
:
1001 ports
+= list(sram
.bus
.fields
.values())
1004 ports
+= list(self
.xics_icp
.bus
.fields
.values())
1005 ports
+= list(self
.xics_ics
.bus
.fields
.values())
1006 ports
.append(self
.int_level_i
)
1009 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
1010 ports
.append(self
.gpio_o
)
1018 class TestIssuer(Elaboratable
):
1019 def __init__(self
, pspec
):
1020 self
.ti
= TestIssuerInternal(pspec
)
1022 self
.pll
= DummyPLL()
1024 # PLL direct clock or not
1025 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
1027 self
.pll_18_o
= Signal(reset_less
=True)
1029 def elaborate(self
, platform
):
1033 # TestIssuer runs at direct clock
1034 m
.submodules
.ti
= ti
= self
.ti
1035 cd_int
= ClockDomain("coresync")
1038 # ClockSelect runs at PLL output internal clock rate
1039 m
.submodules
.pll
= pll
= self
.pll
1041 # add clock domains from PLL
1042 cd_pll
= ClockDomain("pllclk")
1045 # PLL clock established. has the side-effect of running clklsel
1046 # at the PLL's speed (see DomainRenamer("pllclk") above)
1047 pllclk
= ClockSignal("pllclk")
1048 comb
+= pllclk
.eq(pll
.clk_pll_o
)
1050 # wire up external 24mhz to PLL
1051 comb
+= pll
.clk_24_i
.eq(ClockSignal())
1053 # output 18 mhz PLL test signal
1054 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
1056 # now wire up ResetSignals. don't mind them being in this domain
1057 pll_rst
= ResetSignal("pllclk")
1058 comb
+= pll_rst
.eq(ResetSignal())
1060 # internal clock is set to selector clock-out. has the side-effect of
1061 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1062 intclk
= ClockSignal("coresync")
1064 comb
+= intclk
.eq(pll
.clk_pll_o
)
1066 comb
+= intclk
.eq(ClockSignal())
1071 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
1072 [ClockSignal(), ResetSignal()]
1074 def external_ports(self
):
1075 ports
= self
.ti
.external_ports()
1076 ports
.append(ClockSignal())
1077 ports
.append(ResetSignal())
1079 ports
.append(self
.pll
.clk_sel_i
)
1080 ports
.append(self
.pll_18_o
)
1081 ports
.append(self
.pll
.pll_lck_o
)
1085 if __name__
== '__main__':
1086 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1092 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
1093 imem_ifacetype
='bare_wb',
1098 dut
= TestIssuer(pspec
)
1099 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
1101 if len(sys
.argv
) == 1:
1102 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
1103 with
open("test_issuer.il", "w") as f
: