src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  16                         help="Enable interrupts",
  17                         default=True)
  18     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  19                         help="Disable interrupts",
  20                         default=False)
  21     parser.add_argument("--enable-lessports", dest='lessports',
  22                         action="store_true",
  23                         help="Enable less regfile ports",
  24                         default=True)
  25     parser.add_argument("--disable-lessports", dest='lessports',
  26                         action="store_false",
  27                         help="enable more regfile ports",
  28                         default=False)
  29     parser.add_argument("--enable-core", dest='core', action="store_true",
  30                         help="Enable main core",
  31                         default=True)
  32     parser.add_argument("--disable-core", dest='core', action="store_false",
  33                         help="disable main core",
  34                         default=False)
  35     parser.add_argument("--enable-mmu", dest='mmu', action="store_true",
  36                         help="Enable mmu",
  37                         default=False)
  38     parser.add_argument("--disable-mmu", dest='mmu', action="store_false",
  39                         help="Disable mmu",
  40                         default=False)
  41     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  42                         help="Enable pll",
  43                         default=False)
  44     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  45                         help="Disable pll",
  46                         default=False)
  47     parser.add_argument("--enable-testgpio", action="store_true",
  48                         help="Disable gpio pins",
  49                         default=False)
  50     parser.add_argument("--enable-sram4x4kblock", action="store_true",
  51                         help="Disable sram 4x4k block",
  52                         default=False)
  53     parser.add_argument("--debug", default="jtag", help="Select debug " \
  54                         "interface [jtag | dmi] [default jtag]")
  55     parser.add_argument("--enable-svp64", dest='svp64', action="store_true",
  56                         help="Enable SVP64",
  57                         default=True)
  58     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
  59                         help="disable SVP64",
  60                         default=False)
  61
  62     args = parser.parse_args()
  63
  64     print(args)
  65
  66     units = {'alu': 1,
  67              'cr': 1, 'branch': 1, 'trap': 1,
  68              'logical': 1,
  69              'spr': 1,
  70              'div': 1,
  71              'mul': 1,
  72              'shiftrot': 1
  73             }
  74     if args.mmu:
  75         units['mmu'] = 1 # enable MMU
  76
  77     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  78                          imem_ifacetype='bare_wb',
  79                          addr_wid=48,
  80                          mask_wid=8,
  81                          # must leave at 64
  82                          reg_wid=64,
  83                          # set to 32 for instruction-memory width=32
  84                          imem_reg_wid=64,
  85                          # set to 32 to make data wishbone bus 32-bit
  86                          #wb_data_wid=32,
  87                          xics=args.xics, # XICS interrupt controller
  88                          nocore=not args.core, # test coriolis2 ioring
  89                          regreduce = args.lessports, # less regfile ports
  90                          use_pll=args.pll,  # bypass PLL
  91                          gpio=args.enable_testgpio, # for test purposes
  92                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
  93                          debug=args.debug,      # set to jtag or dmi
  94                          svp64=args.svp64,      # enable SVP64
  95                          mmu=args.mmu,          # enable MMU
  96                          units=units)
  97
  98     print("mmu", pspec.__dict__["mmu"])
  99     print("nocore", pspec.__dict__["nocore"])
 100     print("regreduce", pspec.__dict__["regreduce"])
 101     print("gpio", pspec.__dict__["gpio"])
 102     print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
 103     print("xics", pspec.__dict__["xics"])
 104     print("use_pll", pspec.__dict__["use_pll"])
 105     print("debug", pspec.__dict__["debug"])
 106     print("SVP64", pspec.__dict__["svp64"])
 107
 108     dut = TestIssuer(pspec)
 109
 110     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
 111     with open(args.output_filename, "w") as f:
 112         f.write(vl)