src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from openpower.decoder.isa.caller import special_sprs
  13 from openpower.decoder.power_decoder import create_pdecode
  14 from openpower.decoder.power_decoder2 import PowerDecode2
  15 from openpower.decoder.selectable_int import SelectableInt
  16 from openpower.decoder.isa.all import ISA
  17
  18 # note that using SPRreduced has to be done to match the
  19 # PowerDecoder2 SPR map
  20 from openpower.decoder.power_enums import SPRreduced as SPR
  21 from openpower.decoder.power_enums import spr_dict, Function, XER_bits
  22 from soc.config.test.test_loadstore import TestMemPspec
  23 from openpower.endian import bigendian
  24
  25 from soc.simple.core import NonProductionCore
  26 from soc.experiment.compalu_multi import find_ok  # hack
  27
  28 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  29                                                  check_sim_memory)
  30
  31 # test with ALU data and Logical data
  32 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  33 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  34 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  35 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  36 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  37 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  38 from openpower.util import spr_to_fast_reg
  39
  40 # list of SPRs that are controlled and managed by the MMU
  41 mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
  42
  43 def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
  44         fsm = core.fus.get_fu("mmu0").alu
  45         yield fsm.mmu.l_in.mtspr.eq(1)
  46         yield fsm.mmu.l_in.sprn.eq(i)
  47         yield fsm.mmu.l_in.rs.eq(val)
  48         yield
  49         yield fsm.mmu.l_in.mtspr.eq(0)
  50         print("mmu_spr was updated")
  51
  52 def setup_regs(pdecode2, core, test):
  53
  54     # set up INT regfile, "direct" write (bypass rd/write ports)
  55     intregs = core.regs.int
  56     for i in range(32):
  57         if intregs.unary:
  58             yield intregs.regs[i].reg.eq(test.regs[i])
  59         else:
  60             yield intregs.memory._array[i].eq(test.regs[i])
  61     yield Settle()
  62
  63     # set up CR regfile, "direct" write across all CRs
  64     cr = test.cr
  65     crregs = core.regs.cr
  66     #cr = int('{:32b}'.format(cr)[::-1], 2)
  67     print("setup cr reg", hex(cr))
  68     for i in range(8):
  69         #j = 7-i
  70         cri = (cr >> (i*4)) & 0xf
  71         #cri = int('{:04b}'.format(cri)[::-1], 2)
  72         print("setup cr reg", hex(cri), i,
  73               crregs.regs[i].reg.shape())
  74         yield crregs.regs[i].reg.eq(cri)
  75
  76     # set up XER.  "direct" write (bypass rd/write ports)
  77     xregs = core.regs.xer
  78     print("setup sprs", test.sprs)
  79     xer = None
  80     if 'XER' in test.sprs:
  81         xer = test.sprs['XER']
  82     if 1 in test.sprs:
  83         xer = test.sprs[1]
  84     if xer is not None:
  85         if isinstance(xer, int):
  86             xer = SelectableInt(xer, 64)
  87         sobit = xer[XER_bits['SO']].value
  88         yield xregs.regs[xregs.SO].reg.eq(sobit)
  89         cabit = xer[XER_bits['CA']].value
  90         ca32bit = xer[XER_bits['CA32']].value
  91         yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
  92         ovbit = xer[XER_bits['OV']].value
  93         ov32bit = xer[XER_bits['OV32']].value
  94         yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
  95         print("setting XER so %d ca %d ca32 %d ov %d ov32 %d" %
  96               (sobit, cabit, ca32bit, ovbit, ov32bit))
  97     else:
  98         yield xregs.regs[xregs.SO].reg.eq(0)
  99         yield xregs.regs[xregs.OV].reg.eq(0)
 100         yield xregs.regs[xregs.CA].reg.eq(0)
 101
 102     # setting both fast and slow SPRs from test data
 103
 104     fregs = core.regs.fast
 105     sregs = core.regs.spr
 106     for sprname, val in test.sprs.items():
 107         if isinstance(val, SelectableInt):
 108             val = val.value
 109         if isinstance(sprname, int):
 110             sprname = spr_dict[sprname].SPR
 111         if sprname == 'XER':
 112             continue
 113         fast = spr_to_fast_reg(sprname)
 114         if fast is None:
 115             # match behaviour of SPRMap in power_decoder2.py
 116             for i, x in enumerate(SPR):
 117                 if sprname == x.name:
 118                     print("setting slow SPR %d (%s) to %x" %
 119                           (i, sprname, val))
 120                     if not sprname in mmu_sprs:
 121                         yield sregs.memory._array[i].eq(val)
 122                     else:
 123                         yield from set_mmu_spr(sprname, i, val, core)
 124         else:
 125             print("setting fast reg %d (%s) to %x" %
 126                   (fast, sprname, val))
 127             if fregs.unary:
 128                 rval = fregs.int.regs[fast].reg
 129             else:
 130                 rval = fregs.memory._array[fast]
 131             yield rval.eq(val)
 132
 133     # allow changes to settle before reporting on XER
 134     yield Settle()
 135
 136     # XER
 137     so = yield xregs.regs[xregs.SO].reg
 138     ov = yield xregs.regs[xregs.OV].reg
 139     ca = yield xregs.regs[xregs.CA].reg
 140     oe = yield pdecode2.e.do.oe.oe
 141     oe_ok = yield pdecode2.e.do.oe.oe_ok
 142
 143     print("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
 144     print("oe:", oe, oe_ok)
 145
 146
 147 def check_regs(dut, sim, core, test, code):
 148     # int regs
 149     intregs = []
 150     for i in range(32):
 151         if core.regs.int.unary:
 152             rval = yield core.regs.int.regs[i].reg
 153         else:
 154             rval = yield core.regs.int.memory._array[i]
 155         intregs.append(rval)
 156     print("int regs", list(map(hex, intregs)))
 157     for i in range(32):
 158         simregval = sim.gpr[i].asint()
 159         dut.assertEqual(simregval, intregs[i],
 160                         "int reg %d not equal %s. got %x expected %x" % \
 161                             (i, repr(code), simregval, intregs[i]))
 162
 163     # CRs
 164     crregs = []
 165     for i in range(8):
 166         rval = yield core.regs.cr.regs[i].reg
 167         crregs.append(rval)
 168     print("cr regs", list(map(hex, crregs)))
 169     for i in range(8):
 170         rval = crregs[i]
 171         cri = sim.crl[7-i].get_range().value
 172         print("cr reg", i, hex(cri), i, hex(rval))
 173         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 174         dut.assertEqual(cri, rval,
 175                         "cr reg %d not equal %s" % (i, repr(code)))
 176
 177     # XER
 178     xregs = core.regs.xer
 179     so = yield xregs.regs[xregs.SO].reg
 180     ov = yield xregs.regs[xregs.OV].reg
 181     ca = yield xregs.regs[xregs.CA].reg
 182
 183     print("sim SO", sim.spr['XER'][XER_bits['SO']])
 184     e_so = sim.spr['XER'][XER_bits['SO']].value
 185     e_ov = sim.spr['XER'][XER_bits['OV']].value
 186     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 187     e_ca = sim.spr['XER'][XER_bits['CA']].value
 188     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 189
 190     e_ov = e_ov | (e_ov32 << 1)
 191     e_ca = e_ca | (e_ca32 << 1)
 192
 193     print("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 194     dut.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 195     dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 196     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 197
 198     # Check the PC as well
 199     state = core.regs.state
 200     pc = yield state.r_ports['cia'].o_data
 201     e_pc = sim.pc.CIA.value
 202     dut.assertEqual(e_pc, pc)
 203
 204
 205 def wait_for_busy_hi(cu):
 206     while True:
 207         busy_o = yield cu.busy_o
 208         terminate_o = yield cu.core_terminate_o
 209         if busy_o:
 210             print("busy/terminate:", busy_o, terminate_o)
 211             break
 212         print("!busy", busy_o, terminate_o)
 213         yield
 214
 215
 216 def set_issue(core, dec2, sim):
 217     yield core.issue_i.eq(1)
 218     yield
 219     yield core.issue_i.eq(0)
 220     yield from wait_for_busy_hi(core)
 221
 222
 223 def wait_for_busy_clear(cu):
 224     while True:
 225         busy_o = yield cu.busy_o
 226         terminate_o = yield cu.core_terminate_o
 227         if not busy_o:
 228             print("busy/terminate:", busy_o, terminate_o)
 229             break
 230         print("busy",)
 231         yield
 232
 233
 234 class TestRunner(FHDLTestCase):
 235     def __init__(self, tst_data):
 236         super().__init__("run_all")
 237         self.test_data = tst_data
 238
 239     def run_all(self):
 240         m = Module()
 241         comb = m.d.comb
 242         instruction = Signal(32)
 243         ivalid_i = Signal()
 244
 245         pspec = TestMemPspec(ldst_ifacetype='testpi',
 246                              imem_ifacetype='',
 247                              addr_wid=48,
 248                              mask_wid=8,
 249                              reg_wid=64)
 250
 251         m.submodules.core = core = NonProductionCore(pspec)
 252         pdecode2 = core.pdecode2
 253         l0 = core.l0
 254
 255         comb += core.raw_opcode_i.eq(instruction)
 256         comb += core.ivalid_i.eq(ivalid_i)
 257
 258         # temporary hack: says "go" immediately for both address gen and ST
 259         ldst = core.fus.fus['ldst0']
 260         m.d.comb += ldst.ad.go.eq(ldst.ad.rel)  # link addr-go direct to rel
 261         m.d.comb += ldst.st.go.eq(ldst.st.rel)  # link store-go direct to rel
 262
 263         # nmigen Simulation
 264         sim = Simulator(m)
 265         sim.add_clock(1e-6)
 266
 267         def process():
 268             yield core.issue_i.eq(0)
 269             yield
 270
 271             for test in self.test_data:
 272                 print(test.name)
 273                 program = test.program
 274                 self.subTest(test.name)
 275                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 276                           test.msr,
 277                           bigendian=bigendian)
 278                 gen = program.generate_instructions()
 279                 instructions = list(zip(gen, program.assembly.splitlines()))
 280
 281                 yield from setup_tst_memory(l0, sim)
 282                 yield from setup_regs(core, test)
 283
 284                 index = sim.pc.CIA.value//4
 285                 while index < len(instructions):
 286                     ins, code = instructions[index]
 287
 288                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 289                     print(code)
 290
 291                     # ask the decoder to decode this binary data (endian'd)
 292                     yield core.bigendian_i.eq(bigendian)  # little / big?
 293                     yield instruction.eq(ins)          # raw binary instr.
 294                     yield ivalid_i.eq(1)
 295                     yield Settle()
 296                     # fn_unit = yield pdecode2.e.fn_unit
 297                     #fuval = self.funit.value
 298                     #self.assertEqual(fn_unit & fuval, fuval)
 299
 300                     # set operand and get inputs
 301                     yield from set_issue(core, pdecode2, sim)
 302                     yield Settle()
 303
 304                     yield from wait_for_busy_clear(core)
 305                     yield ivalid_i.eq(0)
 306                     yield
 307
 308                     print("sim", code)
 309                     # call simulated operation
 310                     opname = code.split(' ')[0]
 311                     yield from sim.call(opname)
 312                     index = sim.pc.CIA.value//4
 313
 314                     # register check
 315                     yield from check_regs(self, sim, core, test, code)
 316
 317                     # Memory check
 318                     yield from check_sim_memory(self, l0, sim, code)
 319
 320         sim.add_sync_process(process)
 321         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 322                            traces=[]):
 323             sim.run()
 324
 325
 326 if __name__ == "__main__":
 327     unittest.main(exit=False)
 328     suite = unittest.TestSuite()
 329     suite.addTest(TestRunner(LDSTTestCase().test_data))
 330     suite.addTest(TestRunner(CRTestCase().test_data))
 331     suite.addTest(TestRunner(ShiftRotTestCase().test_data))
 332     suite.addTest(TestRunner(LogicalTestCase().test_data))
 333     suite.addTest(TestRunner(ALUTestCase().test_data))
 334     suite.addTest(TestRunner(BranchTestCase().test_data))
 335
 336     runner = unittest.TextTestRunner()
 337     runner.run(suite)