testing CRs after writing: not in the right bit-order
[soc.git] / src / soc / simple / test / test_core.py
1 from nmigen import Module, Signal, Cat
2 from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil.formaltest import FHDLTestCase
4 from nmigen.cli import rtlil
5 import unittest
6 from soc.decoder.isa.caller import special_sprs
7 from soc.decoder.power_decoder import create_pdecode
8 from soc.decoder.power_decoder2 import PowerDecode2
9 from soc.decoder.isa.all import ISA
10 from soc.decoder.power_enums import Function, XER_bits
11
12
13 from soc.simple.core import NonProductionCore
14 from soc.experiment.compalu_multi import find_ok # hack
15
16 # test with ALU data and Logical data
17 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
18 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
19 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
20 from soc.fu.cr.test.test_pipe_caller import CRTestCase
21 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
22
23
24 def set_issue(core, dec2, sim):
25 yield core.issue_i.eq(1)
26 yield
27 yield core.issue_i.eq(0)
28 while True:
29 busy_o = yield core.busy_o
30 if busy_o:
31 break
32 print("!busy",)
33 yield
34
35
36 def wait_for_busy_clear(cu):
37 while True:
38 busy_o = yield cu.busy_o
39 if not busy_o:
40 break
41 print("busy",)
42 yield
43
44
45 class TestRunner(FHDLTestCase):
46 def __init__(self, tst_data):
47 super().__init__("run_all")
48 self.test_data = tst_data
49
50 def run_all(self):
51 m = Module()
52 comb = m.d.comb
53 instruction = Signal(32)
54 ivalid_i = Signal()
55
56 m.submodules.core = core = NonProductionCore()
57 pdecode = core.pdecode
58 pdecode2 = core.pdecode2
59
60 comb += pdecode2.dec.raw_opcode_in.eq(instruction)
61 comb += core.ivalid_i.eq(ivalid_i)
62 sim = Simulator(m)
63
64 sim.add_clock(1e-6)
65
66 def process():
67 yield core.issue_i.eq(0)
68 yield
69
70 for test in self.test_data:
71 print(test.name)
72 program = test.program
73 self.subTest(test.name)
74 sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
75 gen = program.generate_instructions()
76 instructions = list(zip(gen, program.assembly.splitlines()))
77
78 # set up INT regfile, "direct" write (bypass rd/write ports)
79 for i in range(32):
80 yield core.regs.int.regs[i].reg.eq(test.regs[i])
81
82 # set up CR regfile, "direct" write across all CRs
83 cr = test.cr
84 print ("cr reg", hex(cr))
85 for i in range(8):
86 cri = (cr>>(i*4)) & 0xf
87 print ("cr reg", hex(cri), i,
88 core.regs.cr.regs[i].reg.shape())
89 yield core.regs.cr.regs[i].reg.eq(cri)
90
91 # set up XER. "direct" write (bypass rd/write ports)
92 xregs = core.regs.xer
93 print ("sprs", test.sprs)
94 if special_sprs['XER'] in test.sprs:
95 xer = test.sprs[special_sprs['XER']]
96 sobit = xer[XER_bits['SO']].asint()
97 yield xregs.regs[xregs.SO].reg.eq(sobit)
98 cabit = xer[XER_bits['CA']].asint()
99 ca32bit = xer[XER_bits['CA32']].asint()
100 yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
101 ovbit = xer[XER_bits['OV']].asint()
102 ov32bit = xer[XER_bits['OV32']].asint()
103 yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
104 else:
105 yield xregs.regs[xregs.SO].reg.eq(0)
106 yield xregs.regs[xregs.OV].reg.eq(0)
107 yield xregs.regs[xregs.CA].reg.eq(0)
108
109 index = sim.pc.CIA.value//4
110 while index < len(instructions):
111 ins, code = instructions[index]
112
113 print("0x{:X}".format(ins & 0xffffffff))
114 print(code)
115
116 # ask the decoder to decode this binary data (endian'd)
117 yield pdecode2.dec.bigendian.eq(0) # little / big?
118 yield instruction.eq(ins) # raw binary instr.
119 yield ivalid_i.eq(1)
120 yield Settle()
121 #fn_unit = yield pdecode2.e.fn_unit
122 #fuval = self.funit.value
123 #self.assertEqual(fn_unit & fuval, fuval)
124
125 # set operand and get inputs
126 yield from set_issue(core, pdecode2, sim)
127 yield Settle()
128
129 yield from wait_for_busy_clear(core)
130 yield ivalid_i.eq(0)
131 yield
132
133 print ("sim", code)
134 # call simulated operation
135 opname = code.split(' ')[0]
136 yield from sim.call(opname)
137 index = sim.pc.CIA.value//4
138
139 # int regs
140 intregs = []
141 for i in range(32):
142 rval = yield core.regs.int.regs[i].reg
143 intregs.append(rval)
144 print ("int regs", list(map(hex, intregs)))
145 for i in range(32):
146 simregval = sim.gpr[i].asint()
147 self.assertEqual(simregval, intregs[i],
148 "int reg %d not equal %s" % (i, repr(code)))
149
150 # CRs
151 crregs = []
152 for i in range(8):
153 rval = yield core.regs.cr.regs[i].reg
154 crregs.append(rval)
155 print ("cr regs", list(map(hex, crregs)))
156 print ("sim cr reg", hex(cr))
157 for i in range(8):
158 rval = crregs[i]
159 cri = sim.crl[7-i].get_range().value
160 print ("cr reg", i, hex(cri), i, hex(rval))
161 self.assertEqual(cri, rval,
162 "cr reg %d not equal %s" % (i, repr(code)))
163
164 sim.add_sync_process(process)
165 with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
166 traces=[]):
167 sim.run()
168
169
170 if __name__ == "__main__":
171 unittest.main(exit=False)
172 suite = unittest.TestSuite()
173 suite.addTest(TestRunner(CRTestCase.test_data))
174 suite.addTest(TestRunner(ShiftRotTestCase.test_data))
175 suite.addTest(TestRunner(LogicalTestCase.test_data))
176 suite.addTest(TestRunner(ALUTestCase.test_data))
177 suite.addTest(TestRunner(BranchTestCase.test_data))
178
179 runner = unittest.TextTestRunner()
180 runner.run(suite)
181