src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.isa.all import ISA
  16 from soc.decoder.power_enums import Function, XER_bits
  17
  18
  19 from soc.simple.core import NonProductionCore
  20 from soc.experiment.compalu_multi import find_ok # hack
  21
  22 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  23                                                  check_sim_memory)
  24
  25 # test with ALU data and Logical data
  26 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  27 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  28 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  29 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  30 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  31 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  32
  33
  34 def setup_regs(core, test):
  35
  36
  37     # set up INT regfile, "direct" write (bypass rd/write ports)
  38     intregs = core.regs.int
  39     for i in range(32):
  40         yield intregs.regs[i].reg.eq(test.regs[i])
  41
  42     # set up CR regfile, "direct" write across all CRs
  43     cr = test.cr
  44     crregs = core.regs.cr
  45     #cr = int('{:32b}'.format(cr)[::-1], 2)
  46     print ("cr reg", hex(cr))
  47     for i in range(8):
  48         #j = 7-i
  49         cri = (cr>>(i*4)) & 0xf
  50         #cri = int('{:04b}'.format(cri)[::-1], 2)
  51         print ("cr reg", hex(cri), i,
  52                 crregs.regs[i].reg.shape())
  53         yield crregs.regs[i].reg.eq(cri)
  54
  55     # set up XER.  "direct" write (bypass rd/write ports)
  56     xregs = core.regs.xer
  57     print ("sprs", test.sprs)
  58     if special_sprs['XER'] in test.sprs:
  59         xer = test.sprs[special_sprs['XER']]
  60         sobit = xer[XER_bits['SO']].value
  61         yield xregs.regs[xregs.SO].reg.eq(sobit)
  62         cabit = xer[XER_bits['CA']].value
  63         ca32bit = xer[XER_bits['CA32']].value
  64         yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
  65         ovbit = xer[XER_bits['OV']].value
  66         ov32bit = xer[XER_bits['OV32']].value
  67         yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
  68     else:
  69         yield xregs.regs[xregs.SO].reg.eq(0)
  70         yield xregs.regs[xregs.OV].reg.eq(0)
  71         yield xregs.regs[xregs.CA].reg.eq(0)
  72
  73     # XER
  74     so = yield xregs.regs[xregs.SO].reg
  75     ov = yield xregs.regs[xregs.OV].reg
  76     ca = yield xregs.regs[xregs.CA].reg
  77     oe = yield pdecode2.e.oe.oe
  78     oe_ok = yield pdecode2.e.oe.oe_ok
  79
  80     print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
  81     print ("oe:", oe, oe_ok)
  82
  83
  84 def check_regs(dut, sim, core, test, code):
  85     # int regs
  86     intregs = []
  87     for i in range(32):
  88         rval = yield core.regs.int.regs[i].reg
  89         intregs.append(rval)
  90     print ("int regs", list(map(hex, intregs)))
  91     for i in range(32):
  92         simregval = sim.gpr[i].asint()
  93         dut.assertEqual(simregval, intregs[i],
  94             "int reg %d not equal %s" % (i, repr(code)))
  95
  96     # CRs
  97     crregs = []
  98     for i in range(8):
  99         rval = yield core.regs.cr.regs[i].reg
 100         crregs.append(rval)
 101     print ("cr regs", list(map(hex, crregs)))
 102     for i in range(8):
 103         rval = crregs[i]
 104         cri = sim.crl[7-i].get_range().value
 105         print ("cr reg", i, hex(cri), i, hex(rval))
 106         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 107         dut.assertEqual(cri, rval,
 108             "cr reg %d not equal %s" % (i, repr(code)))
 109
 110     # XER
 111     xregs = core.regs.xer
 112     so = yield xregs.regs[xregs.SO].reg
 113     ov = yield xregs.regs[xregs.OV].reg
 114     ca = yield xregs.regs[xregs.CA].reg
 115
 116     print ("sim SO", sim.spr['XER'][XER_bits['SO']])
 117     e_so = sim.spr['XER'][XER_bits['SO']].value
 118     e_ov = sim.spr['XER'][XER_bits['OV']].value
 119     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 120     e_ca = sim.spr['XER'][XER_bits['CA']].value
 121     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 122
 123     e_ov = e_ov | (e_ov32<<1)
 124     e_ca = e_ca | (e_ca32<<1)
 125
 126     print ("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 127     dut.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 128     dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 129     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 130
 131
 132 def set_issue(core, dec2, sim):
 133     yield core.issue_i.eq(1)
 134     yield
 135     yield core.issue_i.eq(0)
 136     while True:
 137         busy_o = yield core.busy_o
 138         if busy_o:
 139             break
 140         print("!busy",)
 141         yield
 142
 143
 144 def wait_for_busy_clear(cu):
 145     while True:
 146         busy_o = yield cu.busy_o
 147         if not busy_o:
 148             break
 149         print("busy",)
 150         yield
 151
 152
 153 class TestRunner(FHDLTestCase):
 154     def __init__(self, tst_data):
 155         super().__init__("run_all")
 156         self.test_data = tst_data
 157
 158     def run_all(self):
 159         m = Module()
 160         comb = m.d.comb
 161         instruction = Signal(32)
 162         ivalid_i = Signal()
 163
 164         m.submodules.core = core = NonProductionCore()
 165         pdecode2 = core.pdecode2
 166         l0 = core.l0
 167
 168         comb += core.raw_opcode_i.eq(instruction)
 169         comb += core.ivalid_i.eq(ivalid_i)
 170
 171         # temporary hack: says "go" immediately for both address gen and ST
 172         ldst = core.fus.fus['ldst0']
 173         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
 174         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
 175
 176         # nmigen Simulation
 177         sim = Simulator(m)
 178         sim.add_clock(1e-6)
 179
 180         def process():
 181             yield core.issue_i.eq(0)
 182             yield
 183
 184             for test in self.test_data:
 185                 print(test.name)
 186                 program = test.program
 187                 self.subTest(test.name)
 188                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 189                           test.msr)
 190                 gen = program.generate_instructions()
 191                 instructions = list(zip(gen, program.assembly.splitlines()))
 192
 193                 yield from setup_test_memory(l0, sim)
 194                 yield from setup_regs(core, test)
 195
 196                 index = sim.pc.CIA.value//4
 197                 while index < len(instructions):
 198                     ins, code = instructions[index]
 199
 200                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 201                     print(code)
 202
 203                     # ask the decoder to decode this binary data (endian'd)
 204                     yield core.bigendian_i.eq(0)  # little / big?
 205                     yield instruction.eq(ins)          # raw binary instr.
 206                     yield ivalid_i.eq(1)
 207                     yield Settle()
 208                     #fn_unit = yield pdecode2.e.fn_unit
 209                     #fuval = self.funit.value
 210                     #self.assertEqual(fn_unit & fuval, fuval)
 211
 212                     # set operand and get inputs
 213                     yield from set_issue(core, pdecode2, sim)
 214                     yield Settle()
 215
 216                     yield from wait_for_busy_clear(core)
 217                     yield ivalid_i.eq(0)
 218                     yield
 219
 220                     print ("sim", code)
 221                     # call simulated operation
 222                     opname = code.split(' ')[0]
 223                     yield from sim.call(opname)
 224                     index = sim.pc.CIA.value//4
 225
 226                     # register check
 227                     yield from check_regs(self, sim, core, test, code)
 228
 229                     # Memory check
 230                     yield from check_sim_memory(self, l0, sim, code)
 231
 232         sim.add_sync_process(process)
 233         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 234                             traces=[]):
 235             sim.run()
 236
 237
 238 if __name__ == "__main__":
 239     unittest.main(exit=False)
 240     suite = unittest.TestSuite()
 241     suite.addTest(TestRunner(LDSTTestCase.test_data))
 242     suite.addTest(TestRunner(CRTestCase.test_data))
 243     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 244     suite.addTest(TestRunner(LogicalTestCase.test_data))
 245     suite.addTest(TestRunner(ALUTestCase.test_data))
 246     suite.addTest(TestRunner(BranchTestCase.test_data))
 247
 248     runner = unittest.TextTestRunner()
 249     runner.run(suite)
 250