src/soc/simple/test/test_core.py

   1 from nmigen import Module, Signal, Cat
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import special_sprs
   7 from soc.decoder.power_decoder import create_pdecode
   8 from soc.decoder.power_decoder2 import PowerDecode2
   9 from soc.decoder.isa.all import ISA
  10 from soc.decoder.power_enums import Function, XER_bits
  11
  12
  13 from soc.simple.core import NonProductionCore
  14 from soc.experiment.compalu_multi import find_ok # hack
  15
  16 # test with ALU data and Logical data
  17 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  18 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  19 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  20 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  21 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  22
  23
  24 def set_issue(core, dec2, sim):
  25     yield core.issue_i.eq(1)
  26     yield
  27     yield core.issue_i.eq(0)
  28     while True:
  29         busy_o = yield core.busy_o
  30         if busy_o:
  31             break
  32         print("!busy",)
  33         yield
  34
  35
  36 def wait_for_busy_clear(cu):
  37     while True:
  38         busy_o = yield cu.busy_o
  39         if not busy_o:
  40             break
  41         print("busy",)
  42         yield
  43
  44
  45 class TestRunner(FHDLTestCase):
  46     def __init__(self, tst_data):
  47         super().__init__("run_all")
  48         self.test_data = tst_data
  49
  50     def run_all(self):
  51         m = Module()
  52         comb = m.d.comb
  53         instruction = Signal(32)
  54         ivalid_i = Signal()
  55
  56         m.submodules.core = core = NonProductionCore()
  57         pdecode = core.pdecode
  58         pdecode2 = core.pdecode2
  59
  60         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  61         comb += core.ivalid_i.eq(ivalid_i)
  62         sim = Simulator(m)
  63
  64         sim.add_clock(1e-6)
  65
  66         def process():
  67             yield core.issue_i.eq(0)
  68             yield
  69
  70             for test in self.test_data:
  71                 print(test.name)
  72                 program = test.program
  73                 self.subTest(test.name)
  74                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr)
  75                 gen = program.generate_instructions()
  76                 instructions = list(zip(gen, program.assembly.splitlines()))
  77
  78                 # set up INT regfile, "direct" write (bypass rd/write ports)
  79                 for i in range(32):
  80                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
  81
  82                 # set up CR regfile, "direct" write across all CRs
  83                 cr = test.cr
  84                 #cr = int('{:32b}'.format(cr)[::-1], 2)
  85                 print ("cr reg", hex(cr))
  86                 for i in range(8):
  87                     #j = 7-i
  88                     cri = (cr>>(i*4)) & 0xf
  89                     #cri = int('{:04b}'.format(cri)[::-1], 2)
  90                     print ("cr reg", hex(cri), i,
  91                             core.regs.cr.regs[i].reg.shape())
  92                     yield core.regs.cr.regs[i].reg.eq(cri)
  93
  94                 # set up XER.  "direct" write (bypass rd/write ports)
  95                 xregs = core.regs.xer
  96                 print ("sprs", test.sprs)
  97                 if special_sprs['XER'] in test.sprs:
  98                     xer = test.sprs[special_sprs['XER']]
  99                     sobit = xer[XER_bits['SO']].asint()
 100                     yield xregs.regs[xregs.SO].reg.eq(sobit)
 101                     cabit = xer[XER_bits['CA']].asint()
 102                     ca32bit = xer[XER_bits['CA32']].asint()
 103                     yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
 104                     ovbit = xer[XER_bits['OV']].asint()
 105                     ov32bit = xer[XER_bits['OV32']].asint()
 106                     yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
 107                 else:
 108                     yield xregs.regs[xregs.SO].reg.eq(0)
 109                     yield xregs.regs[xregs.OV].reg.eq(0)
 110                     yield xregs.regs[xregs.CA].reg.eq(0)
 111
 112                 index = sim.pc.CIA.value//4
 113                 while index < len(instructions):
 114                     ins, code = instructions[index]
 115
 116                     print("0x{:X}".format(ins & 0xffffffff))
 117                     print(code)
 118
 119                     # ask the decoder to decode this binary data (endian'd)
 120                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 121                     yield instruction.eq(ins)          # raw binary instr.
 122                     yield ivalid_i.eq(1)
 123                     yield Settle()
 124                     #fn_unit = yield pdecode2.e.fn_unit
 125                     #fuval = self.funit.value
 126                     #self.assertEqual(fn_unit & fuval, fuval)
 127
 128                     # set operand and get inputs
 129                     yield from set_issue(core, pdecode2, sim)
 130                     yield Settle()
 131
 132                     yield from wait_for_busy_clear(core)
 133                     yield ivalid_i.eq(0)
 134                     yield
 135
 136                     print ("sim", code)
 137                     # call simulated operation
 138                     opname = code.split(' ')[0]
 139                     yield from sim.call(opname)
 140                     index = sim.pc.CIA.value//4
 141
 142                     # int regs
 143                     intregs = []
 144                     for i in range(32):
 145                         rval = yield core.regs.int.regs[i].reg
 146                         intregs.append(rval)
 147                     print ("int regs", list(map(hex, intregs)))
 148                     for i in range(32):
 149                         simregval = sim.gpr[i].asint()
 150                         self.assertEqual(simregval, intregs[i],
 151                             "int reg %d not equal %s" % (i, repr(code)))
 152
 153                     # CRs
 154                     crregs = []
 155                     for i in range(8):
 156                         rval = yield core.regs.cr.regs[i].reg
 157                         crregs.append(rval)
 158                     print ("cr regs", list(map(hex, crregs)))
 159                     print ("sim cr reg", hex(cr))
 160                     for i in range(8):
 161                         rval = crregs[i]
 162                         cri = sim.crl[7-i].get_range().value
 163                         print ("cr reg", i, hex(cri), i, hex(rval))
 164                         self.assertEqual(cri, rval,
 165                             "cr reg %d not equal %s" % (i, repr(code)))
 166
 167         sim.add_sync_process(process)
 168         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 169                             traces=[]):
 170             sim.run()
 171
 172
 173 if __name__ == "__main__":
 174     unittest.main(exit=False)
 175     suite = unittest.TestSuite()
 176     suite.addTest(TestRunner(CRTestCase.test_data))
 177     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 178     #suite.addTest(TestRunner(LogicalTestCase.test_data))
 179     #suite.addTest(TestRunner(ALUTestCase.test_data))
 180     #suite.addTest(TestRunner(BranchTestCase.test_data))
 181
 182     runner = unittest.TextTestRunner()
 183     runner.run(suite)
 184