src/soc/simple/test/test_core.py

   1 """simple core test
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_decoder2 import PowerDecode2
  15 from soc.decoder.isa.all import ISA
  16 from soc.decoder.power_enums import Function, XER_bits
  17
  18
  19 from soc.simple.core import NonProductionCore
  20 from soc.experiment.compalu_multi import find_ok # hack
  21
  22 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  23                                                  check_sim_memory)
  24
  25 # test with ALU data and Logical data
  26 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  27 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  28 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  29 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  30 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  31 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  32
  33
  34 def set_issue(core, dec2, sim):
  35     yield core.issue_i.eq(1)
  36     yield
  37     yield core.issue_i.eq(0)
  38     while True:
  39         busy_o = yield core.busy_o
  40         if busy_o:
  41             break
  42         print("!busy",)
  43         yield
  44
  45
  46 def wait_for_busy_clear(cu):
  47     while True:
  48         busy_o = yield cu.busy_o
  49         if not busy_o:
  50             break
  51         print("busy",)
  52         yield
  53
  54
  55 class TestRunner(FHDLTestCase):
  56     def __init__(self, tst_data):
  57         super().__init__("run_all")
  58         self.test_data = tst_data
  59
  60     def run_all(self):
  61         m = Module()
  62         comb = m.d.comb
  63         instruction = Signal(32)
  64         ivalid_i = Signal()
  65
  66         m.submodules.core = core = NonProductionCore()
  67         pdecode2 = core.pdecode2
  68         l0 = core.l0
  69
  70         comb += core.raw_opcode_i.eq(instruction)
  71         comb += core.ivalid_i.eq(ivalid_i)
  72
  73         # temporary hack: says "go" immediately for both address gen and ST
  74         ldst = core.fus.fus['ldst0']
  75         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  76         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  77
  78         # nmigen Simulation
  79         sim = Simulator(m)
  80         sim.add_clock(1e-6)
  81
  82         def process():
  83             yield core.issue_i.eq(0)
  84             yield
  85
  86             for test in self.test_data:
  87                 print(test.name)
  88                 program = test.program
  89                 self.subTest(test.name)
  90                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
  91                           test.msr)
  92                 gen = program.generate_instructions()
  93                 instructions = list(zip(gen, program.assembly.splitlines()))
  94
  95                 yield from setup_test_memory(l0, sim)
  96
  97                 # set up INT regfile, "direct" write (bypass rd/write ports)
  98                 for i in range(32):
  99                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
 100
 101                 # set up CR regfile, "direct" write across all CRs
 102                 cr = test.cr
 103                 #cr = int('{:32b}'.format(cr)[::-1], 2)
 104                 print ("cr reg", hex(cr))
 105                 for i in range(8):
 106                     #j = 7-i
 107                     cri = (cr>>(i*4)) & 0xf
 108                     #cri = int('{:04b}'.format(cri)[::-1], 2)
 109                     print ("cr reg", hex(cri), i,
 110                             core.regs.cr.regs[i].reg.shape())
 111                     yield core.regs.cr.regs[i].reg.eq(cri)
 112
 113                 # set up XER.  "direct" write (bypass rd/write ports)
 114                 xregs = core.regs.xer
 115                 print ("sprs", test.sprs)
 116                 if special_sprs['XER'] in test.sprs:
 117                     xer = test.sprs[special_sprs['XER']]
 118                     sobit = xer[XER_bits['SO']].value
 119                     yield xregs.regs[xregs.SO].reg.eq(sobit)
 120                     cabit = xer[XER_bits['CA']].value
 121                     ca32bit = xer[XER_bits['CA32']].value
 122                     yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
 123                     ovbit = xer[XER_bits['OV']].value
 124                     ov32bit = xer[XER_bits['OV32']].value
 125                     yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
 126                 else:
 127                     yield xregs.regs[xregs.SO].reg.eq(0)
 128                     yield xregs.regs[xregs.OV].reg.eq(0)
 129                     yield xregs.regs[xregs.CA].reg.eq(0)
 130
 131                 index = sim.pc.CIA.value//4
 132                 while index < len(instructions):
 133                     ins, code = instructions[index]
 134
 135                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 136                     print(code)
 137
 138                     # ask the decoder to decode this binary data (endian'd)
 139                     yield core.bigendian_i.eq(0)  # little / big?
 140                     yield instruction.eq(ins)          # raw binary instr.
 141                     yield ivalid_i.eq(1)
 142                     yield Settle()
 143                     #fn_unit = yield pdecode2.e.fn_unit
 144                     #fuval = self.funit.value
 145                     #self.assertEqual(fn_unit & fuval, fuval)
 146
 147                     # XER
 148                     so = yield xregs.regs[xregs.SO].reg
 149                     ov = yield xregs.regs[xregs.OV].reg
 150                     ca = yield xregs.regs[xregs.CA].reg
 151                     oe = yield pdecode2.e.oe.oe
 152                     oe_ok = yield pdecode2.e.oe.oe_ok
 153
 154                     print ("before: so/ov-32/ca-32", so, bin(ov), bin(ca))
 155                     print ("oe:", oe, oe_ok)
 156
 157                     # set operand and get inputs
 158                     yield from set_issue(core, pdecode2, sim)
 159                     yield Settle()
 160
 161                     yield from wait_for_busy_clear(core)
 162                     yield ivalid_i.eq(0)
 163                     yield
 164
 165                     print ("sim", code)
 166                     # call simulated operation
 167                     opname = code.split(' ')[0]
 168                     yield from sim.call(opname)
 169                     index = sim.pc.CIA.value//4
 170
 171                     # int regs
 172                     intregs = []
 173                     for i in range(32):
 174                         rval = yield core.regs.int.regs[i].reg
 175                         intregs.append(rval)
 176                     print ("int regs", list(map(hex, intregs)))
 177                     for i in range(32):
 178                         simregval = sim.gpr[i].asint()
 179                         self.assertEqual(simregval, intregs[i],
 180                             "int reg %d not equal %s" % (i, repr(code)))
 181
 182                     # CRs
 183                     crregs = []
 184                     for i in range(8):
 185                         rval = yield core.regs.cr.regs[i].reg
 186                         crregs.append(rval)
 187                     print ("cr regs", list(map(hex, crregs)))
 188                     print ("sim cr reg", hex(cr))
 189                     for i in range(8):
 190                         rval = crregs[i]
 191                         cri = sim.crl[7-i].get_range().value
 192                         print ("cr reg", i, hex(cri), i, hex(rval))
 193                         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=363
 194                         self.assertEqual(cri, rval,
 195                             "cr reg %d not equal %s" % (i, repr(code)))
 196
 197                     # XER
 198                     so = yield xregs.regs[xregs.SO].reg
 199                     ov = yield xregs.regs[xregs.OV].reg
 200                     ca = yield xregs.regs[xregs.CA].reg
 201
 202                     print ("sim SO", sim.spr['XER'][XER_bits['SO']])
 203                     e_so = sim.spr['XER'][XER_bits['SO']].value
 204                     e_ov = sim.spr['XER'][XER_bits['OV']].value
 205                     e_ov32 = sim.spr['XER'][XER_bits['OV32']].value
 206                     e_ca = sim.spr['XER'][XER_bits['CA']].value
 207                     e_ca32 = sim.spr['XER'][XER_bits['CA32']].value
 208
 209                     e_ov = e_ov | (e_ov32<<1)
 210                     e_ca = e_ca | (e_ca32<<1)
 211
 212                     print ("after: so/ov-32/ca-32", so, bin(ov), bin(ca))
 213                     self.assertEqual(e_so, so, "so mismatch %s" % (repr(code)))
 214                     self.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
 215                     self.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 216
 217                     # Memory check
 218                     yield from check_sim_memory(self, l0, sim, code)
 219
 220         sim.add_sync_process(process)
 221         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
 222                             traces=[]):
 223             sim.run()
 224
 225
 226 if __name__ == "__main__":
 227     unittest.main(exit=False)
 228     suite = unittest.TestSuite()
 229     suite.addTest(TestRunner(LDSTTestCase.test_data))
 230     suite.addTest(TestRunner(CRTestCase.test_data))
 231     suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 232     suite.addTest(TestRunner(LogicalTestCase.test_data))
 233     suite.addTest(TestRunner(ALUTestCase.test_data))
 234     suite.addTest(TestRunner(BranchTestCase.test_data))
 235
 236     runner = unittest.TextTestRunner()
 237     runner.run(suite)
 238