src/soc/simple/test/test_issuer_mmu.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 # test with MMU
  22 from openpower.test.mmu.mmu_cases import MMUTestCase
  23 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  24 from openpower.test.ldst.ldst_cases import LDSTTestCase
  25 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
  26 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  27
  28 from openpower.simulator.program import Program
  29 from openpower.endian import bigendian
  30 from openpower.test.common import TestAccumulatorBase
  31
  32 class MMUTestCase(TestAccumulatorBase):
  33
  34     def case_1_dcbz(self):
  35         lst = ["dcbz 1, 2",
  36                "dcbz 1, 3"]
  37         initial_regs = [0] * 32
  38         initial_regs[1] = 0x0004
  39         initial_regs[2] = 0x0008
  40         initial_regs[3] = 0x0007
  41         initial_mem = {}
  42         self.add_case(Program(lst, bigendian), initial_regs,
  43                              initial_mem=initial_mem)
  44
  45 if __name__ == "__main__":
  46     svp64 = True
  47     if len(sys.argv) == 2:
  48         if sys.argv[1] == 'nosvp64':
  49             svp64 = False
  50         sys.argv.pop()
  51
  52     print ("SVP64 test mode enabled", svp64)
  53
  54     unittest.main(exit=False)
  55     suite = unittest.TestSuite()
  56
  57     # MMU/DCache integration tests
  58     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
  59                               microwatt_mmu=False))
  60
  61     runner = unittest.TextTestRunner()
  62     runner.run(suite)