src/soc/simple/test/test_issuer_mmu_ifetch.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 #@platen:bookmarks
  22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
  23
  24 # test with MMU
  25 from openpower.test.mmu.mmu_cases import MMUTestCase
  26 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  27 from openpower.test.ldst.ldst_cases import LDSTTestCase
  28 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
  29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  30
  31 from openpower.simulator.program import Program
  32 from openpower.endian import bigendian
  33 from openpower.test.common import TestAccumulatorBase
  34
  35 from openpower.consts import MSR
  36
  37 from soc.experiment.test import pagetables
  38
  39
  40 class MMUTestCase(TestAccumulatorBase):
  41
  42     def case_virtual_ld_st(self):
  43         lst = ["stb 10,0(2)",
  44                "addi 10,0, -4",
  45                "stb 10,0(5)",
  46                "lhz 6,0(2)",
  47               ]
  48
  49         # set up regs
  50         initial_regs = [0] * 32
  51         initial_regs[1] = 0x1000000 # hm, was going to do mtspr 720,1 with this
  52         initial_regs[2] = 0x3456
  53         initial_regs[3] = 0x4321
  54         initial_regs[4] = 0x6543
  55         initial_regs[5] = 0x3457
  56         initial_regs[10] = 0xfe
  57
  58         # no pre-loaded memory here
  59         initial_mem = {}
  60
  61         # set virtual and non-privileged
  62         initial_msr = 0 << MSR.PR # must set "problem" state
  63         #initial_msr |= 1 << MSR.DR # set "virtual" state for data
  64         initial_msr |= 1 << MSR.IR # set "virtual" state for instructions
  65         initial_msr |= 1 << MSR.LE # set little-endian
  66
  67         # set PRTBL to 0x1000000
  68         initial_sprs = {720: 0x1000000} # PRTBL
  69
  70         print("MMUTEST: initial_msr=",initial_msr)
  71         self.add_case(Program(lst, bigendian), initial_regs,
  72                              initial_mem=initial_mem,
  73                              initial_sprs=initial_sprs,
  74                              initial_msr=initial_msr)
  75
  76     def case_virtual_invalid_no_prtbl(self):
  77         """virtual memory test but with no PRTBL set it is expected
  78         to throw an "invalid" exception
  79         """
  80         lst = ["stb 10,0(2)",
  81               ]
  82
  83         # set up regs
  84         initial_regs = [0] * 32
  85
  86         # set virtual and non-privileged
  87         initial_msr = 1 << MSR.PR # must set "problem" state
  88         initial_msr |= 1 << MSR.DR # set "virtual" state for data
  89         initial_msr |= 1 << MSR.IR # set "virtual" state for instructions
  90
  91         print("MMUTEST: initial_msr=",initial_msr)
  92         self.add_case(Program(lst, bigendian), initial_regs,
  93                              initial_msr=initial_msr,
  94                              stop_at_pc=0x400) # stop at this exception addr
  95
  96 if __name__ == "__main__":
  97     svp64 = True
  98     if len(sys.argv) == 2:
  99         if sys.argv[1] == 'nosvp64':
 100             svp64 = False
 101         sys.argv.pop()
 102
 103     print ("SVP64 test mode enabled", svp64)
 104
 105     unittest.main(exit=False)
 106     suite = unittest.TestSuite()
 107
 108     # MMU/DCache integration tests
 109     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
 110                               microwatt_mmu=True,
 111                               rom=pagetables.test1))
 112
 113     runner = unittest.TextTestRunner()
 114     runner.run(suite)