src/soc/simple/test/test_issuer_mmu_microwatt.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 #@platen:bookmarks
  22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
  23
  24 # test with MMU
  25 from openpower.test.mmu.mmu_cases import MMUTestCase
  26 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  27 from openpower.test.ldst.ldst_cases import LDSTTestCase
  28 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
  29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  30 from soc.experiment.test import pagetables
  31
  32
  33 from openpower.simulator.program import Program
  34 from openpower.endian import bigendian
  35 from openpower.test.common import TestAccumulatorBase
  36
  37 from openpower.consts import MSR
  38
  39 from soc.experiment.test import pagetables
  40
  41
  42 class MMUTestCase(TestAccumulatorBase):
  43
  44     def case_microwatt_test_3_mmu_ld(self):
  45         lst = [
  46                "ld 6,0(2)",
  47               ]
  48
  49         # set up regs
  50         initial_regs = [0] * 32
  51         initial_regs[2] = 0x124108
  52
  53         # memory same as microwatt test
  54         initial_mem = pagetables.microwatt_test2
  55
  56         # set virtual and non-privileged
  57         # msr: 8000000000000011
  58         initial_msr = 0 << MSR.PR # must set "problem" state
  59         initial_msr |= 1 << MSR.LE # little-endian
  60         initial_msr |= 1 << MSR.SF # 64-bit
  61         initial_msr |= 1 << MSR.DR # set "virtual" state for data
  62
  63         # set PRTBL to 0x12000
  64         initial_sprs = {720: 0x12000, # PRTBL
  65                         48: 1       # PIDR
  66                         }
  67
  68         print("MMUTEST: initial_msr=",initial_msr)
  69         self.add_case(Program(lst, bigendian), initial_regs,
  70                              initial_mem=initial_mem,
  71                              initial_sprs=initial_sprs,
  72                              initial_msr=initial_msr)
  73
  74
  75 if __name__ == "__main__":
  76     svp64 = True
  77     if len(sys.argv) == 2:
  78         if sys.argv[1] == 'nosvp64':
  79             svp64 = False
  80         sys.argv.pop()
  81
  82     print ("SVP64 test mode enabled", svp64)
  83
  84     unittest.main(exit=False)
  85     suite = unittest.TestSuite()
  86
  87     # MMU/DCache integration tests
  88     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
  89                               microwatt_mmu=True,
  90                               rom=pagetables.microwatt_test2))
  91
  92     runner = unittest.TextTestRunner()
  93     runner.run(suite)