src/soc/simulator/test_mul_sim.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.decoder.power_decoder import (create_pdecode)
   6 from soc.decoder.power_enums import (Function, InternalOp,
   7                                      In1Sel, In2Sel, In3Sel,
   8                                      OutSel, RC, LdstLen, CryIn,
   9                                      single_bit_flags, Form, SPR,
  10                                      get_signal_name, get_csv)
  11 from soc.decoder.power_decoder2 import (PowerDecode2)
  12 from soc.simulator.program import Program
  13 from soc.simulator.qemu import run_program
  14 from soc.decoder.isa.all import ISA
  15 from soc.fu.test.common import TestCase
  16 from soc.simulator.test_sim import DecoderBase
  17
  18
  19
  20 class MulTestCases(FHDLTestCase):
  21     test_data = []
  22
  23     def __init__(self, name="div"):
  24         super().__init__(name)
  25         self.test_name = name
  26
  27     def test_mullw(self):
  28         lst = [f"addi 1, 0, 0x5678",
  29                f"addi 2, 0, 0x1234",
  30                f"mullw 3, 1, 2"]
  31         self.run_tst_program(Program(lst), [3])
  32
  33     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  34                                     initial_mem=None):
  35         initial_regs = [0] * 32
  36         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
  37                                             initial_mem, 0)
  38         self.test_data.append(tc)
  39
  40
  41 class MulDecoderTestCase(DecoderBase, MulTestCases):
  42     pass
  43
  44
  45 if __name__ == "__main__":
  46     unittest.main()