src/soc/simulator/test_sim.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.simulator.internalop_sim import InternalOpSimulator
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_enums import (Function, InternalOp,
   8                                      In1Sel, In2Sel, In3Sel,
   9                                      OutSel, RC, LdstLen, CryIn,
  10                                      single_bit_flags, Form, SPR,
  11                                      get_signal_name, get_csv)
  12 from soc.decoder.power_decoder2 import (PowerDecode2)
  13 from soc.simulator.gas import get_assembled_instruction
  14 from soc.simulator.program import Program
  15
  16
  17 class Register:
  18     def __init__(self, num):
  19         self.num = num
  20
  21
  22
  23 class DecoderTestCase(FHDLTestCase):
  24
  25     def run_tst(self, generator, simulator):
  26         m = Module()
  27         comb = m.d.comb
  28         instruction = Signal(32)
  29
  30         pdecode = create_pdecode()
  31
  32         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  33         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  34         sim = Simulator(m)
  35         gen = generator.generate_instructions()
  36
  37         def process():
  38             for ins in gen:
  39
  40                 print("0x{:X}".format(ins & 0xffffffff))
  41
  42                 # ask the decoder to decode this binary data (endian'd)
  43                 yield pdecode2.dec.bigendian.eq(0)  # little / big?
  44                 yield instruction.eq(ins)          # raw binary instr.
  45                 yield Delay(1e-6)
  46                 yield from simulator.execute_op(pdecode2)
  47
  48         sim.add_process(process)
  49         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  50                            traces=[pdecode2.ports()]):
  51             sim.run()
  52
  53     def test_example(self):
  54         lst = ["addi 1, 0, 0x1234",
  55                "addi 2, 0, 0x5678",
  56                "add  3, 1, 2",
  57                "and  4, 1, 2"]
  58         gen = Program(lst)
  59
  60         simulator = InternalOpSimulator()
  61
  62         self.run_tst(gen, simulator)
  63         simulator.regfile.assert_gprs(
  64             {1: 0x1234,
  65              2: 0x5678,
  66              3: 0x68ac,
  67              4: 0x1230})
  68
  69     def test_ldst(self):
  70         lst = ["addi 1, 0, 0x1234",
  71                "addi 2, 0, 0x5678",
  72                "stw  1, 0(2)",
  73                "lwz  3, 0(2)"]
  74         gen = Program(lst)
  75
  76         simulator = InternalOpSimulator()
  77
  78         self.run_tst(gen, simulator)
  79         simulator.regfile.assert_gprs(
  80             {1: 0x1234,
  81              2: 0x5678,
  82              3: 0x1234})
  83
  84     def test_ldst_extended(self):
  85         lst = ["addi 1, 0, 0x1234",
  86                "addi 2, 0, 0x5678",
  87                "addi 4, 0, 0x40",
  88                "stw  1, 0x40(2)",
  89                "lwzx  3, 4, 2"]
  90         gen = Program(lst)
  91
  92         simulator = InternalOpSimulator()
  93
  94         self.run_tst(gen, simulator)
  95         simulator.regfile.assert_gprs(
  96             {1: 0x1234,
  97              2: 0x5678,
  98              3: 0x1234})
  99     def test_ldst_widths(self):
 100         lst = [" lis 1, 0xdead",
 101                "ori 1, 1, 0xbeef",
 102                "addi 2, 0, 0x1000",
 103                "std 1, 0(2)",
 104                "lbz 1, 5(2)",
 105                "lhz 3, 4(2)",
 106                "lwz 4, 4(2)",
 107                "ori 5, 0, 0x12",
 108                "stb 5, 5(2)",
 109                "ld  5, 0(2)"]
 110         gen = Program(lst)
 111         simulator = InternalOpSimulator()
 112         self.run_tst(gen, simulator)
 113         simulator.regfile.assert_gprs({
 114             1: 0xad,
 115             3: 0xdead,
 116             4: 0xdeadbeef,
 117             5: 0xffffffffde12beef})  # checked with qemu
 118
 119
 120 if __name__ == "__main__":
 121     unittest.main()