src/soc/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and
   8 creates an EXT001-encoded "svp64 prefix" followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  15 """
  16
  17 import os, sys
  18 from collections import OrderedDict
  19
  20 from soc.decoder.pseudo.pagereader import ISA
  21 from soc.decoder.power_enums import get_csv, find_wiki_dir
  22
  23
  24 # identifies register by type
  25 def is_CR_3bit(regname):
  26     return regname in ['BF', 'BFA']
  27
  28 def is_CR_5bit(regname):
  29     return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
  30
  31 def is_GPR(regname):
  32     return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
  33
  34 def get_regtype(regname):
  35     if is_CR_3bit(regname):
  36         return "CR_3bit"
  37     if is_CR_5bit(regname):
  38         return "CR_5bit"
  39     if is_GPR(regname):
  40         return "GPR"
  41
  42 # decode GPR into sv extra
  43 def  get_extra_gpr(etype, regmode, field):
  44     if regmode == 'scalar':
  45         # cut into 2-bits 5-bits SS FFFFF
  46         sv_extra = field >> 5
  47         field = field & 0b11111
  48     else:
  49         # cut into 5-bits 2-bits FFFFF SS
  50         sv_extra = field & 0b11
  51         field = field >> 2
  52     return sv_extra, field
  53
  54
  55 # decode 3-bit CR into sv extra
  56 def  get_extra_cr_3bit(etype, regmode, field):
  57     if regmode == 'scalar':
  58         # cut into 2-bits 3-bits SS FFF
  59         sv_extra = field >> 3
  60         field = field & 0b111
  61     else:
  62         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  63         sv_extra = field & 0b1111
  64         field = field >> 4
  65     return sv_extra, field
  66
  67
  68 # decodes SUBVL
  69 def decode_subvl(encoding):
  70     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  71     assert encoding in pmap, \
  72         "encoding %s for SUBVL not recognised" % encoding
  73     return pmap[encoding]
  74
  75
  76 # decodes elwidth
  77 def decode_elwidth(encoding):
  78     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  79     assert encoding in pmap, \
  80         "encoding %s for elwidth not recognised" % encoding
  81     return pmap[encoding]
  82
  83
  84 # decodes predicate register encoding
  85 def decode_predicate(encoding):
  86     pmap = { # integer
  87             '1<<r3': (0, 0b001),
  88             'r3'   : (0, 0b010),
  89             '~r3'   : (0, 0b011),
  90             'r10'   : (0, 0b100),
  91             '~r10'  : (0, 0b101),
  92             'r30'   : (0, 0b110),
  93             '~r30'  : (0, 0b111),
  94             # CR
  95             'lt'    : (1, 0b000),
  96             'nl'    : (1, 0b001), 'ge'    : (1, 0b001), # same value
  97             'gt'    : (1, 0b010),
  98             'ng'    : (1, 0b011), 'le'    : (1, 0b011), # same value
  99             'eq'    : (1, 0b100),
 100             'ne'    : (1, 0b101),
 101             'so'    : (1, 0b110), 'un'    : (1, 0b110), # same value
 102             'ns'    : (1, 0b111), 'nu'    : (1, 0b111), # same value
 103            }
 104     assert encoding in pmap, \
 105         "encoding %s for predicate not recognised" % encoding
 106     return pmap[encoding]
 107
 108
 109 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 110 def decode_bo(encoding):
 111     pmap = { # TODO: double-check that these are the same as Branch BO
 112             'lt'    : 0b000,
 113             'nl'    : 0b001, 'ge'    : 0b001, # same value
 114             'gt'    : 0b010,
 115             'ng'    : 0b011, 'le'    : 0b011, # same value
 116             'eq'    : 0b100,
 117             'ne'    : 0b101,
 118             'so'    : 0b110, 'un'    : 0b110, # same value
 119             'ns'    : 0b111, 'nu'    : 0b111, # same value
 120            }
 121     assert encoding in pmap, \
 122         "encoding %s for BO Mode not recognised" % encoding
 123     return pmap[encoding]
 124
 125 # partial-decode fail-first mode
 126 def decode_ffirst(encoding):
 127     if encoding in ['RC1', '~RC1']:
 128         return encoding
 129     return decode_bo(encoding)
 130
 131
 132 # gets SVP64 ReMap information
 133 class SVP64RM:
 134     def __init__(self):
 135         self.instrs = {}
 136         pth = find_wiki_dir()
 137         for fname in os.listdir(pth):
 138             if fname.startswith("RM"):
 139                 for entry in get_csv(fname):
 140                     self.instrs[entry['insn']] = entry
 141
 142
 143 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 144 class SVP64:
 145     def __init__(self, lst):
 146         self.lst = lst
 147         self.trans = self.translate(lst)
 148
 149     def __iter__(self):
 150         for insn in self.trans:
 151             yield insn
 152
 153     def translate(self, lst):
 154         isa = ISA() # reads the v3.0B pseudo-code markdown files
 155         svp64 = SVP64RM() # reads the svp64 Remap entries for registers
 156         res = []
 157         for insn in lst:
 158             # find first space, to get opcode
 159             ls = insn.split(' ')
 160             opcode = ls[0]
 161             # now find opcode fields
 162             fields = ''.join(ls[1:]).split(',')
 163             fields = list(map(str.strip, fields))
 164             print ("opcode, fields", ls, opcode, fields)
 165
 166             # identify if is a svp64 mnemonic
 167             if not opcode.startswith('sv.'):
 168                 res.append(insn) # unaltered
 169                 continue
 170             opcode = opcode[3:] # strip leading "sv."
 171
 172             # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 173             opmodes = opcode.split("/") # split at "/"
 174             v30b_op = opmodes.pop(0)    # first is the v3.0B
 175             # check instruction ends with dot
 176             rc_mode = v30b_op.endswith('.')
 177             if rc_mode:
 178                 v30b_op = v30b_op[:-1]
 179
 180             if v30b_op not in isa.instr:
 181                 raise Exception("opcode %s of '%s' not supported" % \
 182                                 (v30b_op, insn))
 183             if v30b_op not in svp64.instrs:
 184                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
 185                                 (v30b_op, insn))
 186             v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
 187             rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 188             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 189             print ("v3.0B regs", opcode, v30b_regs)
 190             print (rm)
 191
 192             # right.  the first thing to do is identify the ordering of
 193             # the registers, by name.  the EXTRA2/3 ordering is in
 194             # rm['0']..rm['3'] but those fields contain the names RA, BB
 195             # etc.  we have to read the pseudocode to understand which
 196             # reg is which in our instruction. sigh.
 197
 198             # first turn the svp64 rm into a "by name" dict, recording
 199             # which position in the RM EXTRA it goes into
 200             # also: record if the src or dest was a CR, for sanity-checking
 201             # (elwidth overrides on CRs are banned)
 202             dest_reg_cr, src_reg_cr = False, False
 203             svp64_reg_byname = {}
 204             for i in range(4):
 205                 rfield = rm[str(i)]
 206                 if not rfield or rfield == '0':
 207                     continue
 208                 print ("EXTRA field", i, rfield)
 209                 rfield = rfield.split(";") # s:RA;d:CR1 etc.
 210                 for r in rfield:
 211                     rtype = r[0]
 212                     # TODO: ignoring s/d makes it impossible to do
 213                     # LD/ST-with-update.
 214                     r = r[2:] # ignore s: and d:
 215                     svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
 216                     # check the regtype (if CR, record that)
 217                     regtype = get_regtype(r)
 218                     if regtype in ['CR_3bit', 'CR_5bit']:
 219                         if rtype == 'd':
 220                             dest_reg_cr = True
 221                         if rtype == 'd':
 222                             src_reg_cr = True
 223
 224             print ("EXTRA field index, by regname", svp64_reg_byname)
 225
 226             # okaaay now we identify the field value (opcode N,N,N) with
 227             # the pseudo-code info (opcode RT, RA, RB)
 228             assert len(fields) == len(v30b_regs), \
 229                 "length of fields %s must match insn `%s`" % \
 230                         (str(v30b_regs), insn)
 231             opregfields = zip(fields, v30b_regs) # err that was easy
 232
 233             # now for each of those find its place in the EXTRA encoding
 234             extras = OrderedDict()
 235             for idx, (field, regname) in enumerate(opregfields):
 236                 extra = svp64_reg_byname.get(regname, None)
 237                 regtype = get_regtype(regname)
 238                 extras[extra] = (idx, field, regname, regtype)
 239                 print ("    ", extra, extras[extra])
 240
 241             # great! got the extra fields in their associated positions:
 242             # also we know the register type. now to create the EXTRA encodings
 243             etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
 244             ptype = rm['Ptype'] # Predication type: Twin / Single
 245             extra_bits = 0
 246             v30b_newfields = []
 247             for extra_idx, (idx, field, regname, regtype) in extras.items():
 248                 # is it a field we don't alter/examine?  if so just put it
 249                 # into newfields
 250                 if regtype is None:
 251                     v30b_newfields.append(field)
 252
 253                 # first, decode the field number. "5.v" or "3.s" or "9"
 254                 field = field.split(".")
 255                 regmode = 'scalar' # default
 256                 if len(field) == 2:
 257                     if field[1] == 's':
 258                         regmode = 'scalar'
 259                     elif field[1] == 'v':
 260                         regmode = 'vector'
 261                 field = int(field[0]) # actual register number
 262                 print ("    ", regmode, field, end=" ")
 263
 264                 # XXX TODO: the following is a bit of a laborious repeated
 265                 # mess, which could (and should) easily be parameterised.
 266
 267                 # encode SV-GPR field into extra, v3.0field
 268                 if regtype == 'GPR':
 269                     sv_extra, field = get_extra_gpr(etype, regmode, field)
 270                     # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 271                     # (and shrink to a single bit if ok)
 272                     if etype == 'EXTRA2':
 273                         if regmode == 'scalar':
 274                             # range is r0-r63 in increments of 1
 275                             assert (sv_extra >> 1) == 0, \
 276                                 "scalar GPR %s cannot fit into EXTRA2 %s" % \
 277                                     (regname, str(extras[extra_idx]))
 278                             # all good: encode as scalar
 279                             sv_extra = sv_extra & 0b01
 280                         else:
 281                             # range is r0-r127 in increments of 4
 282                             assert sv_extra & 0b01 == 0, \
 283                                 "vector field %s cannot fit into EXTRA2 %s" % \
 284                                     (regname, str(extras[extra_idx]))
 285                             # all good: encode as vector (bit 2 set)
 286                             sv_extra = 0b10 | (sv_extra >> 1)
 287                     elif regmode == 'vector':
 288                         # EXTRA3 vector bit needs marking
 289                         sv_extra |= 0b100
 290
 291                 # encode SV-CR 3-bit field into extra, v3.0field
 292                 elif regtype == 'CR_3bit':
 293                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 294                     # now sanity-check (and shrink afterwards)
 295                     if etype == 'EXTRA2':
 296                         if regmode == 'scalar':
 297                             # range is CR0-CR15 in increments of 1
 298                             assert (sv_extra >> 1) == 0, \
 299                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 300                                     (regname, str(extras[extra_idx]))
 301                             # all good: encode as scalar
 302                             sv_extra = sv_extra & 0b01
 303                         else:
 304                             # range is CR0-CR127 in increments of 16
 305                             assert sv_extra & 0b111 == 0, \
 306                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 307                                     (regname, str(extras[extra_idx]))
 308                             # all good: encode as vector (bit 2 set)
 309                             sv_extra = 0b10 | (sv_extra >> 3)
 310                     else:
 311                         if regmode == 'scalar':
 312                             # range is CR0-CR31 in increments of 1
 313                             assert (sv_extra >> 2) == 0, \
 314                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 315                                     (regname, str(extras[extra_idx]))
 316                             # all good: encode as scalar
 317                             sv_extra = sv_extra & 0b11
 318                         else:
 319                             # range is CR0-CR127 in increments of 8
 320                             assert sv_extra & 0b11 == 0, \
 321                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 322                                     (regname, str(extras[extra_idx]))
 323                             # all good: encode as vector (bit 3 set)
 324                             sv_extra = 0b100 | (sv_extra >> 2)
 325
 326                 # encode SV-CR 5-bit field into extra, v3.0field
 327                 # *sigh* this is the same as 3-bit except the 2 LSBs are
 328                 # passed through
 329                 elif regtype == 'CR_5bit':
 330                     cr_subfield = field & 0b11
 331                     field = field >> 2 # strip bottom 2 bits
 332                     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 333                     # now sanity-check (and shrink afterwards)
 334                     if etype == 'EXTRA2':
 335                         if regmode == 'scalar':
 336                             # range is CR0-CR15 in increments of 1
 337                             assert (sv_extra >> 1) == 0, \
 338                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 339                                     (regname, str(extras[extra_idx]))
 340                             # all good: encode as scalar
 341                             sv_extra = sv_extra & 0b01
 342                         else:
 343                             # range is CR0-CR127 in increments of 16
 344                             assert sv_extra & 0b111 == 0, \
 345                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 346                                     (regname, str(extras[extra_idx]))
 347                             # all good: encode as vector (bit 2 set)
 348                             sv_extra = 0b10 | (sv_extra >> 3)
 349                     else:
 350                         if regmode == 'scalar':
 351                             # range is CR0-CR31 in increments of 1
 352                             assert (sv_extra >> 2) == 0, \
 353                                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 354                                     (regname, str(extras[extra_idx]))
 355                             # all good: encode as scalar
 356                             sv_extra = sv_extra & 0b11
 357                         else:
 358                             # range is CR0-CR127 in increments of 8
 359                             assert sv_extra & 0b11 == 0, \
 360                                 "vector CR %s cannot fit into EXTRA2 %s" % \
 361                                     (regname, str(extras[extra_idx]))
 362                             # all good: encode as vector (bit 3 set)
 363                             sv_extra = 0b100 | (sv_extra >> 2)
 364
 365                     # reconstruct the actual 5-bit CR field
 366                     field = (field << 2) | cr_subfield
 367
 368                 # capture the extra field info
 369                 print ("=>", "%5s" % bin(sv_extra), field)
 370                 extras[extra_idx] = sv_extra
 371
 372                 # append altered field value to v3.0b
 373                 v30b_newfields.append(str(field))
 374
 375             print ("new v3.0B fields", v30b_op, v30b_newfields)
 376             print ("extras", extras)
 377
 378             # rright.  now we have all the info. start creating SVP64 RM
 379             svp64_rm = 0b0
 380
 381             # begin with EXTRA fields
 382             for idx, sv_extra in extras.items():
 383                 if idx is None: continue
 384                 # start at bit 10, work up 2/3 times EXTRA idx
 385                 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 386                 svp64_rm |= sv_extra << (10+idx*offs)
 387
 388             # parts of svp64_rm
 389             mmode = 0  # bit 0
 390             pmask = 0  # bits 1-3
 391             destwid = 0 # bits 4-5
 392             srcwid = 0 # bits 6-7
 393             subvl = 0   # bits 8-9
 394             smask = 0 # bits 16-18 but only for twin-predication
 395             mode = 0 # bits 19-23
 396
 397             has_pmask = False
 398             has_smask = False
 399
 400             saturation = None
 401             src_zero = 0
 402             dst_zero = 0
 403             sv_mode = None
 404
 405             mapreduce = False
 406             mapreduce_crm = False
 407             mapreduce_svm = False
 408
 409             predresult = False
 410             failfirst = False
 411
 412             # ok let's start identifying opcode augmentation fields
 413             for encmode in opmodes:
 414                 # predicate mask (dest)
 415                 if encmode.startswith("m="):
 416                     pme = encmode
 417                     pmmode, pmask = decode_predicate(encmode[2:])
 418                     mmode = pmmode
 419                     has_pmask = True
 420                 # predicate mask (src, twin-pred)
 421                 elif encmode.startswith("sm="):
 422                     sme = encmode
 423                     smmode, smask = decode_predicate(encmode[3:])
 424                     mmode = smmode
 425                     has_smask = True
 426                 # vec2/3/4
 427                 elif encmode.startswith("vec"):
 428                     subvl = decode_subvl(encmode[3:])
 429                 # elwidth
 430                 elif encmode.startswith("ew="):
 431                     destwid = decode_elwidth(encmode[3:])
 432                 elif encmode.startswith("sw="):
 433                     srcwid = decode_elwidth(encmode[3:])
 434                 # saturation
 435                 elif encmode == 'sats':
 436                     assert sv_mode is None
 437                     saturation = 1
 438                     sv_mode = 0b10
 439                 elif encmode == 'satu':
 440                     assert sv_mode is None
 441                     sv_mode = 0b10
 442                     saturation = 0
 443                 # predicate zeroing
 444                 elif encmode == 'sz':
 445                     src_zero = 1
 446                 elif encmode == 'dz':
 447                     dst_zero = 1
 448                 # failfirst
 449                 elif encmode.startswith("ff="):
 450                     assert sv_mode is None
 451                     sv_mode = 0b01
 452                     failfirst = decode_ffirst(encmode[3:])
 453                 # predicate-result, interestingly same as fail-first
 454                 elif encmode.startswith("pr="):
 455                     assert sv_mode is None
 456                     sv_mode = 0b11
 457                     predresult = decode_ffirst(encmode[3:])
 458                 # map-reduce mode
 459                 elif encmode == 'mr':
 460                     assert sv_mode is None
 461                     sv_mode = 0b00
 462                     mapreduce = True
 463                 elif encmode == 'crm': # CR on map-reduce
 464                     assert sv_mode is None
 465                     sv_mode = 0b00
 466                     mapreduce_crm = True
 467                 elif encmode == 'svm': # sub-vector mode
 468                     mapreduce_svm = True
 469
 470             # sanity-check that 2Pred mask is same mode
 471             if has_pmask and has_smask:
 472                 assert smmode == pmmode, \
 473                     "predicate masks %s and %s must be same reg type" % \
 474                         (pme, sme)
 475
 476             # sanity-check that twin-predication mask only specified in 2P mode
 477             if ptype == '1P':
 478                 assert has_smask == False, \
 479                     "source-mask can only be specified on Twin-predicate ops"
 480
 481             # construct the mode field, doing sanity-checking along the way
 482
 483             if mapreduce_svm:
 484                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 485                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 486
 487             if src_zero:
 488                 assert has_smask, "src zeroing requires a source predicate"
 489             if dst_zero:
 490                 assert has_pmask, "dest zeroing requires a dest predicate"
 491
 492             # "normal" mode
 493             if sv_mode is None:
 494                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 495                 sv_mode = 0b00
 496
 497             # "mapreduce" modes
 498             elif sv_mode == 0b00:
 499                 mode |= (0b1<<2) # sets mapreduce
 500                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
 501                 if mapreduce_crm:
 502                     mode |= (0b1<<4) # sets CRM mode
 503                     assert rc_mode, "CRM only allowed when Rc=1"
 504                 # bit of weird encoding to jam zero-pred or SVM mode in.
 505                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
 506                 if subvl == 0:
 507                     mode |= (src_zero << 3) # predicate src-zeroing
 508                 elif mapreduce_svm:
 509                     mode |= (1 << 3) # SVM mode
 510
 511             # "failfirst" modes
 512             elif sv_mode == 0b01:
 513                 assert dst_zero == 0, "dest-zero not allowed in failfirst mode"
 514                 if failfirst == 'RC1':
 515                     mode |= (0b1<<4) # sets RC1 mode
 516                     mode |= (src_zero << 3) # predicate src-zeroing
 517                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 518                 elif failfirst == '~RC1':
 519                     mode |= (0b1<<4) # sets RC1 mode...
 520                     mode |= (src_zero << 3) # predicate src-zeroing
 521                     mode |= (0b1<<2) # ... with inversion
 522                     assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
 523                 else:
 524                     assert src_zero == 0, "src-zero not allowed in ffirst BO"
 525                     assert rc_mode, "ffirst BO only possible when Rc=1"
 526                     mode |= (failfirst << 2) # set BO
 527
 528             # "saturation" modes
 529             elif sv_mode == 0b10:
 530                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
 531                 mode |= (saturation<<2) # sets signed/unsigned saturation
 532
 533             # "predicate-result" modes.  err... code-duplication from ffirst
 534             elif sv_mode == 0b11:
 535                 assert dst_zero == 0, "dest-zero not allowed in predresult mode"
 536                 if predresult == 'RC1':
 537                     mode |= (0b1<<4) # sets RC1 mode
 538                     mode |= (src_zero << 3) # predicate src-zeroing
 539                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 540                 elif predresult == '~RC1':
 541                     mode |= (0b1<<4) # sets RC1 mode...
 542                     mode |= (src_zero << 3) # predicate src-zeroing
 543                     mode |= (0b1<<2) # ... with inversion
 544                     assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
 545                 else:
 546                     assert src_zero == 0, "src-zero not allowed in pr-mode BO"
 547                     assert rc_mode, "pr-mode BO only possible when Rc=1"
 548                     mode |= (predresult << 2) # set BO
 549
 550             # whewww.... modes all done :)
 551             # now put into svp64_rm
 552             mode |= sv_mode
 553             svp64_rm |= (mode << 19) # mode: bits 19-23
 554
 555             # put in predicate masks into svp64_rm
 556             if ptype == '2P':
 557                 svp64_rm |= (smask << 16) # source pred: bits 16-18
 558             svp64_rm |= (mmode)           # mask mode: bit 0
 559             svp64_rm |= (pmask << 1)      # 1-pred: bits 1-3
 560
 561             # and subvl
 562             svp64_rm += (subvl << 8)      # subvl: bits 8-9
 563
 564             # put in elwidths
 565             svp64_rm += (srcwid << 6)      # srcwid: bits 6-7
 566             svp64_rm += (destwid << 4)     # destwid: bits 4-5
 567
 568             # nice debug printout. (and now for something completely different)
 569             # https://youtu.be/u0WOIwlXE9g?t=146
 570             print ("svp64_rm", hex(svp64_rm), bin(svp64_rm))
 571             print ("    mmode  0    :", bin(mmode))
 572             print ("    pmask  1-3  :", bin(pmask))
 573             print ("    dstwid 4-5  :", bin(destwid))
 574             print ("    srcwid 6-7  :", bin(srcwid))
 575             print ("    subvl  8-9  :", bin(subvl))
 576             print ("    mode   19-23:", bin(mode))
 577             offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
 578             for idx, sv_extra in extras.items():
 579                 if idx is None: continue
 580                 start = (10+idx*offs)
 581                 end = start + offs-1
 582                 print ("    extra%d %2d-%2d:" % (idx, start, end),
 583                         bin(sv_extra))
 584             if ptype == '2P':
 585                 print ("    smask  16-17:", bin(smask))
 586             print ()
 587
 588         return res
 589
 590 if __name__ == '__main__':
 591     isa = SVP64(['slw 3, 1, 4',
 592                  'extsw 5, 3',
 593                  'sv.extsw 5, 3',
 594                  'sv.cmpi 5, 1, 3, 2',
 595                  'sv.setb 5, 31',
 596                  'sv.isel 64.v, 3, 2, 65.v',
 597                  'sv.setb/m=r3/sm=1<<r3 5, 31',
 598                  'sv.setb/vec2 5, 31',
 599                  'sv.setb/sw=8/ew=16 5, 31',
 600                  'sv.extsw./ff=eq 5, 31',
 601                  'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
 602                  'sv.extsw./pr=eq 5.v, 31',
 603                 ])
 604     csvs = SVP64RM()