Allow the formal engine to perform a same-cycle result in the ALU

[soc.git] / src / soc / config / pinouts.py

diff --git a/src/soc/config/pinouts.py b/src/soc/config/pinouts.py
index 03cfa974b957f654512d8ff204ce1262ce7d632f..9ebe4f7cd2ee18f0af9545fef246298a58401095 100644 (file)
--- a/src/soc/config/pinouts.py
+++ b/src/soc/config/pinouts.py
@@ -3,6 +3,8 @@ import sys
 import json
 from pprint import pprint
 from collections import OrderedDict
+from openpower.util import log
+from nmigen.build.dsl import Resource, Subsignal, Pins
 
 
 def _byteify(data, ignore_dicts = False):
@@ -25,7 +27,40 @@ def _byteify(data, ignore_dicts = False):
     return data
 
 
+def get_pinspec_resources(chipname=None, subset=None, conn=None):
+    """get_pinspec_resources - returns an auto-generated list of resources
+    """
+    chip = load_pinouts(chipname)
+    pinmap = chip['pins.map']
+    specs = []
+    for k, bus in chip['pins.specs'].items():
+        k, num = k.lower().split(":")
+        name = '%s%s' % (k, num)
+        if subset is None or name in subset:
+            io = []
+            for pin in bus:
+                pin = pin.lower()
+                pin, pin_dir = pin[:-1], pin[-1] # split pin+ into pin, +
+                pname = '%s_%s' % (name, pin)
+                if pname in pinmap:
+                    newpin = pinmap[pname][2:]
+                    newpin = '_'.join(newpin.split("_")[1:])
+                    # turn direction into nmigen Pins direction format
+                    dirn = {'-': 'i', '+': 'o', '*': 'io'}[pin_dir]
+                # TODO: make assert_width not have to be 1
+                p = Pins(newpin, dir=dirn, conn=conn, assert_width=1)
+                io.append(Subsignal(pin, p))
+            spec = Resource.family(name, num, default_name=name, ios=io)
+            log("pinspec", name, repr(spec))
+            specs.append(spec)
+    return specs
+
+
 def get_pinspecs(chipname=None, subset=None):
+    """get_pinspecs - returns a dictionary of lists of pins for an IO function
+    example: {'uart': ['tx+', 'rx-'],
+             'i2c': ['sda*', 'scl+']}
+    """
     chip = load_pinouts(chipname)
     pinmap = chip['pins.map']
     specs = OrderedDict() # preserve order
@@ -63,7 +98,7 @@ def load_pinouts(chipname=None):
 
     # path is relative to this filename, in the pinmux submodule
     pinmux = os.getenv("PINMUX", "%s/../../../pinmux" % pth)
-    fname = "%s/%s/litex_pinpads.json" % (pinmux, chipname)
+    fname = "%s/%s/fabric_pinpads.json" % (pinmux, chipname)
     with open(fname) as f:
         txt = f.read()
 
@@ -74,7 +109,12 @@ def load_pinouts(chipname=None):
     return chip
 
 if __name__ == '__main__':
-    if sys.argv == 2:
+    # run this with:
+    # git submodule update --init --remote --recursive
+    # make mkpinmux
+    # python3 soc/config/pinouts.py ngi_pointer (or ls180, or other)
+    # it will print out a stack of debug stuff
+    if len(sys.argv) == 2:
         chipname = sys.argv[1]
     else:
         chipname = None
@@ -82,3 +122,5 @@ if __name__ == '__main__':
     for k, v in chip.items():
         print ("\n****", k, "****")
         pprint(v)
+    print ("chipname pinspec resources", sys.argv, chipname)
+    specs = get_pinspec_resources(chipname, subset=None)