increase register number sizes from 5 to 7

[soc.git] / src / soc / decoder / decode2execute1.py

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index cd4285be533d2c182a5c5102dda07940bee43bfe..75b66d3635c724ce91e13198ab9c447fb5e42e46 100644 (file)
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -7,6 +7,7 @@ from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject
 from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
 from soc.consts import TT
+from soc.experiment.mem_types import LDSTException
 
 
 class Data(Record):
@@ -50,6 +51,7 @@ class IssuerDecode2ToOperand(RecordObject):
         self.oe = Data(1, "oe")
         self.input_carry = Signal(CryIn, reset_less=True)
         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
+        self.ldst_exc  = LDSTException("exc")
         self.trapaddr  = Signal(13, reset_less=True)
         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
@@ -81,20 +83,20 @@ class Decode2ToOperand(IssuerDecode2ToOperand):
 
 class Decode2ToExecute1Type(RecordObject):
 
-    def __init__(self, name=None, asmcode=True, opkls=None):
+    def __init__(self, name=None, asmcode=True, opkls=None, do=None):
 
-        if opkls is None:
+        if do is None and opkls is None:
             opkls = Decode2ToOperand
 
         RecordObject.__init__(self, name=name)
 
         if asmcode:
             self.asmcode = Signal(8, reset_less=True) # only for simulator
-        self.write_reg = Data(5, name="rego")
-        self.write_ea = Data(5, name="ea") # for LD/ST in update mode
-        self.read_reg1 = Data(5, name="reg1")
-        self.read_reg2 = Data(5, name="reg2")
-        self.read_reg3 = Data(5, name="reg3")
+        self.write_reg = Data(7, name="rego")
+        self.write_ea = Data(7, name="ea") # for LD/ST in update mode
+        self.read_reg1 = Data(7, name="reg1")
+        self.read_reg2 = Data(7, name="reg2")
+        self.read_reg3 = Data(7, name="reg3")
         self.write_spr = Data(SPR, name="spro")
         self.read_spr1 = Data(SPR, name="spr1")
         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
@@ -113,6 +115,9 @@ class Decode2ToExecute1Type(RecordObject):
         self.write_cr = Data(3, name="cr_out")
 
         # decode operand data
-        print ("decode2execute init", name, opkls)
+        print ("decode2execute init", name, opkls, do)
         #assert name is not None, str(opkls)
-        self.do = opkls(name)
+        if do is not None:
+            self.do = do
+        else:
+            self.do = opkls(name)