+ if name in ['BF', 'BFA']:
+ self.namespace[name] = val
+ else:
+ self.namespace[name] = SelectableInt(val, sig.width)
+
+ self.namespace['XER'] = self.spr['XER']
+ self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
+
+ def handle_carry_(self, inputs, outputs):
+ inv_a = yield self.dec2.e.invert_a
+ if inv_a:
+ inputs[0] = ~inputs[0]
+
+ imm_ok = yield self.dec2.e.imm_data.ok
+ if imm_ok:
+ imm = yield self.dec2.e.imm_data.data
+ inputs.append(SelectableInt(imm, 64))
+ assert len(outputs) >= 1
+ output = outputs[0]
+ gts = [(x > output) for x in inputs]
+ print(gts)
+ cy = 1 if any(gts) else 0
+ self.spr['XER'][XER_bits['CA']] = cy
+
+
+ # 32 bit carry
+ gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
+ for x in inputs]
+ cy32 = 1 if any(gts) else 0
+ self.spr['XER'][XER_bits['CA32']] = cy32
+
+ def handle_overflow(self, inputs, outputs):
+ inv_a = yield self.dec2.e.invert_a
+ if inv_a:
+ inputs[0] = ~inputs[0]
+
+ imm_ok = yield self.dec2.e.imm_data.ok
+ if imm_ok:
+ imm = yield self.dec2.e.imm_data.data
+ inputs.append(SelectableInt(imm, 64))
+ assert len(outputs) >= 1
+ if len(inputs) >= 2:
+ output = outputs[0]
+ input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
+ output_sgn = exts(output.value, output.bits) < 0
+ ov = 1 if input_sgn[0] == input_sgn[1] and \
+ output_sgn != input_sgn[0] else 0
+
+ self.spr['XER'][XER_bits['OV']] = ov
+ so = self.spr['XER'][XER_bits['SO']]
+ so = so | ov
+ self.spr['XER'][XER_bits['SO']] = so
+
+
+
+ def handle_comparison(self, outputs):
+ out = outputs[0]
+ out = exts(out.value, out.bits)
+ zero = SelectableInt(out == 0, 1)
+ positive = SelectableInt(out > 0, 1)
+ negative = SelectableInt(out < 0, 1)
+ SO = self.spr['XER'][XER_bits['SO']]
+ cr_field = selectconcat(negative, positive, zero, SO)
+ self.crl[0].eq(cr_field)
+
+ def set_pc(self, pc_val):
+ self.namespace['NIA'] = SelectableInt(pc_val, 64)
+ self.pc.update(self.namespace)
+