+"""core of the python-based POWER9 simulator
+
+this is part of a cycle-accurate POWER9 simulator. its primary purpose is
+not speed, it is for both learning and educational purposes, as well as
+a method of verifying the HDL.
+"""
+
from functools import wraps
from soc.decoder.orderedset import OrderedSet
from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
def _get_shifter_mask(self, wid, remainder):
shifter = ((self.bytes_per_word - wid) - remainder) * \
8 # bits per byte
+ # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
+ # BE/LE mode?
+ # shifter = remainder * 8
mask = (1 << (wid * 8)) - 1
print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
return shifter, mask
return val
def st(self, addr, v, width=8):
+ staddr = addr
remainder = addr & (self.bytes_per_word - 1)
addr = addr >> self.word_log2
- print("Writing 0x{:x} to addr 0x{:x}/{:x}".format(v, addr, remainder))
+ print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
+ staddr, addr, remainder))
assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
if width != self.bytes_per_word:
if addr in self.mem:
# decoder2 - an instance of power_decoder2
# regfile - a list of initial values for the registers
def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
- initial_mem=None):
+ initial_mem=None, initial_msr=0):
if initial_sprs is None:
initial_sprs = {}
if initial_mem is None:
initial_mem = {}
self.gpr = GPR(decoder2, regfile)
- self.mem = Mem(initial_mem=initial_mem)
+ self.mem = Mem(bytes_per_word=8, initial_mem=initial_mem)
self.pc = PC()
self.spr = SPR(decoder2, initial_sprs)
+ self.msr = SelectableInt(initial_msr, 64) # underlying reg
# TODO, needed here:
# FPR (same as GPR except for FP nums)
# 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
'CR': self.cr,
+ 'MSR': self.msr,
'undefined': self.undefined,
'mode_is_64bit': True,
'SO': XER_bits['SO']
self.decoder = decoder2.dec
self.dec2 = decoder2
+ def TRAP(self, trap_addr=0x700):
+ print ("TRAP: TODO")
+ # store CIA(+4?) in SRR0, set NIA to 0x700
+ # store MSR in SRR1, set MSR to um errr something, have to check spec
+
def memassign(self, ea, sz, val):
self.mem.memassign(ea, sz, val)
self.namespace['XER'] = self.spr['XER']
self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
+ self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
- def handle_carry_(self, inputs, outputs):
+ def handle_carry_(self, inputs, outputs, already_done):
inv_a = yield self.dec2.e.invert_a
if inv_a:
inputs[0] = ~inputs[0]
gts = [(x > output) for x in inputs]
print(gts)
cy = 1 if any(gts) else 0
- self.spr['XER'][XER_bits['CA']] = cy
-
+ if not (1 & already_done):
+ self.spr['XER'][XER_bits['CA']] = cy
+ print ("inputs", inputs)
# 32 bit carry
gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
for x in inputs]
cy32 = 1 if any(gts) else 0
- self.spr['XER'][XER_bits['CA32']] = cy32
+ if not (2 & already_done):
+ self.spr['XER'][XER_bits['CA32']] = cy32
def handle_overflow(self, inputs, outputs):
inv_a = yield self.dec2.e.invert_a
assert len(outputs) >= 1
if len(inputs) >= 2:
output = outputs[0]
+
+ # OV (64-bit)
input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
output_sgn = exts(output.value, output.bits) < 0
ov = 1 if input_sgn[0] == input_sgn[1] and \
output_sgn != input_sgn[0] else 0
+ # OV (32-bit)
+ input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
+ output32_sgn = exts(output.value, 32) < 0
+ ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
+ output32_sgn != input32_sgn[0] else 0
+
self.spr['XER'][XER_bits['OV']] = ov
+ self.spr['XER'][XER_bits['OV32']] = ov32
so = self.spr['XER'][XER_bits['SO']]
so = so | ov
self.spr['XER'][XER_bits['SO']] = so
results = info.func(self, *inputs)
print(results)
+ # detect if CA/CA32 already in outputs (sra*, basically)
+ already_done = 0
+ if info.write_regs:
+ output_names = create_args(info.write_regs)
+ for name in output_names:
+ if name == 'CA':
+ already_done |= 1
+ if name == 'CA32':
+ already_done |= 2
+
+ print ("carry already done?", bin(already_done))
carry_en = yield self.dec2.e.output_carry
if carry_en:
- yield from self.handle_carry_(inputs, results)
- ov_en = yield self.dec2.e.oe
- if ov_en:
+ yield from self.handle_carry_(inputs, results, already_done)
+ ov_en = yield self.dec2.e.oe.oe
+ ov_ok = yield self.dec2.e.oe.ok
+ if ov_en & ov_ok:
yield from self.handle_overflow(inputs, results)
rc_en = yield self.dec2.e.rc.data
if rc_en:
# any modified return results?
if info.write_regs:
- output_names = create_args(info.write_regs)
for name, output in zip(output_names, results):
if isinstance(output, int):
output = SelectableInt(output, 256)
- if name in info.special_regs:
- print('writing special %s' % name, output)
+ if name in ['CA', 'CA32']:
+ if carry_en:
+ print ("writing %s to XER" % name, output)
+ self.spr['XER'][XER_bits[name]] = output.value
+ else:
+ print ("NOT writing %s to XER" % name, output)
+ elif name in info.special_regs:
+ print('writing special %s' % name, output, special_sprs)
if name in special_sprs:
self.spr[name] = output
else:
def inject():
- """ Decorator factory. """
+ """Decorator factory.
+
+ this decorator will "inject" variables into the function's namespace,
+ from the *dictionary* in self.namespace. it therefore becomes possible
+ to make it look like a whole stack of variables which would otherwise
+ need "self." inserted in front of them (*and* for those variables to be
+ added to the instance) "appear" in the function.
+
+ "self.namespace['SI']" for example becomes accessible as just "SI" but
+ *only* inside the function, when decorated.
+ """
def variable_injector(func):
@wraps(func)
def decorator(*args, **kwargs):
except AttributeError:
func_globals = func.func_globals # Earlier versions.
- context = args[0].namespace
+ context = args[0].namespace # variables to be injected
saved_values = func_globals.copy() # Shallow copy of dict.
func_globals.update(context)
result = func(*args, **kwargs)
projects / soc.git / blobdiff