from functools import wraps
from soc.decoder.orderedset import OrderedSet
-from soc.decoder.selectable_int import SelectableInt, selectconcat
+from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
+ selectconcat)
from collections import namedtuple
import math
instruction_info = namedtuple('instruction_info',
- 'func read_regs uninit_regs write_regs op_fields form asmregs')
+ 'func read_regs uninit_regs write_regs ' + \
+ 'special_regs op_fields form asmregs')
+
+special_sprs = {
+ 'LR': 8,
+ 'CTR': 9,
+ 'TAR': 815,
+ 'XER': 0,
+ 'VRSAVE': 256}
def create_args(reglist, extra=None):
self.NIA = self.CIA + SelectableInt(4, 64)
def update(self, namespace):
- self.CIA = self.NIA
+ self.CIA = namespace['NIA'].narrow(64)
self.NIA = self.CIA + SelectableInt(4, 64)
namespace['CIA'] = self.CIA
namespace['NIA'] = self.NIA
+class SPR(dict):
+ def __init__(self, dec2):
+ self.sd = dec2
+ dict.__init__(self)
+
+ def __getitem__(self, key):
+ # if key in special_sprs get the special spr, otherwise return key
+ if isinstance(key, SelectableInt):
+ key = key.value
+ key = special_sprs.get(key, key)
+ if key in self:
+ return dict.__getitem__(self, key)
+ else:
+ import pdb; pdb.set_trace()
+ return SelectableInt(0, 64)
+
+ def __setitem__(self, key, value):
+ if isinstance(key, SelectableInt):
+ key = key.value
+ key = special_sprs.get(key, key)
+ dict.__setitem__(self, key, value)
+
+ def __call__(self, ridx):
+ return self[ridx]
+
+
+
class ISACaller:
# decoder2 - an instance of power_decoder2
# regfile - a list of initial values for the registers
self.gpr = GPR(decoder2, regfile)
self.mem = Mem()
self.pc = PC()
+ self.spr = SPR(decoder2)
+ # TODO, needed here:
+ # FPR (same as GPR except for FP nums)
+ # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
+ # note that mffs, mcrfs, mtfsf "manage" this FPSCR
+ # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
+ # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
+ # 2.3.2 LR (actually SPR #8)
+ # 2.3.3 CTR (actually SPR #9)
+ # 2.3.4 TAR (actually SPR #815)
+ # 3.2.2 p45 XER (actually SPR #0)
+ # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
+
+ # create CR then allow portions of it to be "selectable" (below)
+ self._cr = SelectableInt(0, 64) # underlying reg
+ self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
+
+ # "undefined", just set to variable-bit-width int (use exts "max")
+ self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
+
self.namespace = {'GPR': self.gpr,
'MEM': self.mem,
+ 'SPR': self.spr,
'memassign': self.memassign,
'NIA': self.pc.NIA,
'CIA': self.pc.CIA,
+ 'CR': self.cr,
+ 'undefined': self.undefined,
+ 'mode_is_64bit': True,
}
+ # field-selectable versions of Condition Register TODO check bitranges?
+ self.crl = []
+ for i in range(8):
+ bits = tuple(range((7-i)*4, (8-i)*4))# errr... maybe?
+ _cr = FieldSelectableInt(self.cr, bits)
+ self.crl.append(_cr)
+ self.namespace["CR%d" % i] = _cr
+
self.decoder = decoder2
def memassign(self, ea, sz, val):
# then "yield" fields only from op_fields rather than hard-coded
# list, here.
fields = self.decoder.sigforms[formname]
- for name in fields._fields:
- if name not in ["RA", "RB", "RT"]:
+ for name in op_fields:
+ if name == 'spr':
+ sig = getattr(fields, name.upper())
+ else:
sig = getattr(fields, name)
- val = yield sig
- self.namespace[name] = SelectableInt(val, sig.width)
+ val = yield sig
+ self.namespace[name] = SelectableInt(val, sig.width)
def call(self, name):
# TODO, asmregs is from the spec, e.g. add RT,RA,RB
info = self.instrs[name]
yield from self.prep_namespace(info.form, info.op_fields)
- input_names = create_args(info.read_regs | info.uninit_regs)
+ # preserve order of register names
+ input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
print(input_names)
+ # main registers (RT, RA ...)
inputs = []
for name in input_names:
regnum = yield getattr(self.decoder, name)
self.namespace[regname] = regnum
print('reading reg %d' % regnum)
inputs.append(self.gpr(regnum))
+
+ # "special" registers
+ for special in info.special_regs:
+ if special in special_sprs:
+ inputs.append(self.spr[special])
+ else:
+ inputs.append(self.namespace[special])
+
print(inputs)
results = info.func(self, *inputs)
print(results)
+ # any modified return results?
if info.write_regs:
output_names = create_args(info.write_regs)
for name, output in zip(output_names, results):
- regnum = yield getattr(self.decoder, name)
- print('writing reg %d' % regnum)
- if output.bits > 64:
- output = SelectableInt(output.value, 64)
- self.gpr[regnum] = output
+ if name in info.special_regs:
+ print('writing special %s' % name, output)
+ if name in special_sprs:
+ self.spr[name] = output
+ else:
+ self.namespace[name].eq(output)
+ else:
+ regnum = yield getattr(self.decoder, name)
+ print('writing reg %d' % regnum)
+ if output.bits > 64:
+ output = SelectableInt(output.value, 64)
+ self.gpr[regnum] = output
+
+ # update program counter
self.pc.update(self.namespace)
context = args[0].namespace
saved_values = func_globals.copy() # Shallow copy of dict.
func_globals.update(context)
-
result = func(*args, **kwargs)
+ args[0].namespace = func_globals
#exec (func.__code__, func_globals)
#finally:
projects / soc.git / blobdiff