selectconcat)
from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
- OutSel)
+ OutSel, CROutSel)
from soc.decoder.helpers import exts, gtu, ltu, undefined
from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
from soc.decoder.power_svp64 import SVP64RM, decode_extra
return retval
+
+# see qemu/target/ppc/mmu-radix64.c for reference
+class RADIX:
+ def __init__(self, mem, caller):
+ self.mem = mem
+ self.caller = caller
+
+ def ld(self, address, width=8, swap=True, check_in_mem=False):
+ print("RADIX: ld from addr 0x{:x} width {:d}".format(address, width))
+
+ pte = self._walk_tree()
+ # use pte to caclculate phys address
+ #mem.ld(address,width,swap,check_in_mem)
+
+ # TODO implement
+ # def st(self, addr, v, width=8, swap=True):
+ # def memassign(self, addr, sz, val):
+ def _next_level(self):
+ return True
+ ## DSISR_R_BADCONFIG
+ ## read_entry
+ ## DSISR_NOPTE
+ ## Prepare for next iteration
+
+ def _walk_tree(self):
+ # walk tree starts on prtbl
+ while True:
+ ret = self._next_level()
+ if ret: return ret
+
class Mem:
def __init__(self, row_bytes=8, initial_mem=None):
class PC:
def __init__(self, pc_init=0):
self.CIA = SelectableInt(pc_init, 64)
- self.NIA = self.CIA + SelectableInt(4, 64)
+ self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
- def update(self, namespace):
+ def update_nia(self, is_svp64):
+ increment = 8 if is_svp64 else 4
+ self.NIA = self.CIA + SelectableInt(increment, 64)
+
+ def update(self, namespace, is_svp64):
+ """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
+ """
self.CIA = namespace['NIA'].narrow(64)
- self.NIA = self.CIA + SelectableInt(4, 64)
+ self.update_nia(is_svp64)
namespace['CIA'] = self.CIA
namespace['NIA'] = self.NIA
self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
+ # these cover the same extra field, split into parts as EXTRA2
+ self.extra2 = list(range(4))
+ self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
+ self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
+ self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
+ self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
+ self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
+ # and here as well, but EXTRA3
+ self.extra3 = list(range(3))
+ self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
+ self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
+ self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
+
+
+SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)
+SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)
+SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)
+SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)
+SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)
+SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)
+SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)
+SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)
+SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)
# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
self.rm = FieldSelectableInt(self.insn, rmfields)
+SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
+SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
+SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
+
+
class SPR(dict):
def __init__(self, dec2, initial_sprs={}):
self.sd = dec2
return None, False
+def get_pdecode_cr_out(dec2, name):
+ op = dec2.dec.op
+ out_sel = yield op.cr_out
+ out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
+ sv_cr_out = yield op.sv_cr_out
+ spec = yield dec2.crout_svdec.spec
+ sv_override = yield dec2.dec_cr_out.sv_override
+ # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
+ out = yield dec2.e.write_cr.data
+ o_isvec = yield dec2.o_isvec
+ print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
+ print (" sv_cr_out", sv_cr_out)
+ print (" cr_bf", out_bitfield)
+ print (" spec", spec)
+ print (" override", sv_override)
+ # identify which regnames map to out / o2
+ if name == 'CR0':
+ if out_sel == CROutSel.CR0.value:
+ return out, o_isvec
+ print ("get_pdecode_idx_out not found", name)
+ return None, False
+
+
def get_pdecode_idx_out(dec2, name):
op = dec2.dec.op
out_sel = yield op.out_sel
# set up registers, instruction memory, data memory, PC, SPRs, MSR
self.svp64rm = SVP64RM()
- self.svstate = SVP64State(initial_svstate)
+ if isinstance(initial_svstate, int):
+ initial_svstate = SVP64State(initial_svstate)
+ self.svstate = initial_svstate
self.gpr = GPR(decoder2, self, self.svstate, regfile)
self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
so = so | ov
self.spr['XER'][XER_bits['SO']] = so
- def handle_comparison(self, outputs):
+ def handle_comparison(self, outputs, cr_idx=0):
out = outputs[0]
assert isinstance(out, SelectableInt), \
"out zero not a SelectableInt %s" % repr(outputs)
SO = self.spr['XER'][XER_bits['SO']]
print("handle_comparison SO", SO)
cr_field = selectconcat(negative, positive, zero, SO)
- self.crl[0].eq(cr_field)
+ self.crl[cr_idx].eq(cr_field)
def set_pc(self, pc_val):
self.namespace['NIA'] = SelectableInt(pc_val, 64)
- self.pc.update(self.namespace)
+ self.pc.update(self.namespace, self.is_svp64_mode)
def setup_one(self):
"""set up one instruction
yield self.dec2.dec.bigendian.eq(self.bigendian)
yield self.dec2.state.msr.eq(self.msr.value)
yield self.dec2.state.pc.eq(pc)
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
# SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
yield Settle()
opcode = yield self.dec2.dec.opcode_in
- pfx = SVP64PrefixFields()
+ pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
pfx.insn.value = opcode
major = pfx.major.asint(msb0=True) # MSB0 inversion
print ("prefix test: opcode:", major, bin(major),
self.is_svp64_mode = ((major == 0b000001) and
pfx.insn[7].value == 0b1 and
pfx.insn[9].value == 0b1)
+ self.pc.update_nia(self.is_svp64_mode)
if not self.is_svp64_mode:
return
# in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
- sv_rm = pfx.rm.asint()
+ print (" svstate.vl", self.svstate.vl.asint(msb0=True))
+ print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
+ sv_rm = pfx.rm.asint(msb0=True)
ins = self.imem.ld(pc+4, 4, False, True)
print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
opname = code.split(' ')[0]
yield from self.call(opname)
+ # don't use this except in special circumstances
if not self.respect_pc:
self.fake_pc += 4
+
print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
def get_assembly_name(self):
if instr_is_privileged and self.msr[MSRb.PR] == 1:
self.TRAP(0x700, PIb.PRIV)
self.namespace['NIA'] = self.trap_nia
- self.pc.update(self.namespace)
+ self.pc.update(self.namespace, self.is_svp64_mode)
return
# check halted condition
print("illegal", name, asmop)
self.TRAP(0x700, PIb.ILLEG)
self.namespace['NIA'] = self.trap_nia
- self.pc.update(self.namespace)
+ self.pc.update(self.namespace, self.is_svp64_mode)
print("name %s != %s - calling ILLEGAL trap, PC: %x" %
(name, asmop, self.pc.CIA.value))
return
dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
+ # get SVSTATE srcstep. TODO: dststep (twin predication)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ vl = self.svstate.vl.asint(msb0=True)
+ mvl = self.svstate.maxvl.asint(msb0=True)
+
+ # VL=0 in SVP64 mode means "do nothing: skip instruction"
+ if self.is_svp64_mode and vl == 0:
+ self.pc.update(self.namespace, self.is_svp64_mode)
+ print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+ return
+
# main input registers (RT, RA ...)
inputs = []
for name in input_names:
# doing this is not part of svp64, it's because output
# registers, to be modified, need to be in the namespace.
regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
+ # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
+ # XXX already done by PowerDecoder2, now
+ #if is_vec:
+ # regnum += srcstep # TODO, elwidth overrides
+
# in case getting the register number is needed, _RA, _RB
regname = "_" + name
self.namespace[regname] = regnum
# clear trap (trap) NIA
self.trap_nia = None
- print(inputs)
+ print("inputs", inputs)
results = info.func(self, *inputs)
- print(results)
+ print("results", results)
# "inject" decorator takes namespace from function locals: we need to
# overwrite NIA being overwritten (sigh)
else:
rc_en = False
if rc_en:
- self.handle_comparison(results)
+ regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
+ self.handle_comparison(results, regnum)
# any modified return results?
if info.write_regs:
output = SelectableInt(output.value, 64)
self.gpr[regnum] = output
- print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+ # check if it is the SVSTATE.src/dest step that needs incrementing
+ # this is our Sub-Program-Counter loop from 0 to VL-1
+ if self.is_svp64_mode:
+ # XXX twin predication TODO
+ vl = self.svstate.vl.asint(msb0=True)
+ mvl = self.svstate.maxvl.asint(msb0=True)
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ print (" svstate.vl", vl)
+ print (" svstate.mvl", mvl)
+ print (" svstate.srcstep", srcstep)
+ # check if srcstep needs incrementing by one, stop PC advancing
+ # svp64 loop can end early if the dest is scalar
+ svp64_dest_vector = not (yield self.dec2.no_out_vec)
+ if svp64_dest_vector and srcstep != vl-1:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ self.pc.NIA.value = self.pc.CIA.value
+ self.namespace['NIA'] = self.pc.NIA
+ print("end of sub-pc call", self.namespace['CIA'],
+ self.namespace['NIA'])
+ return # DO NOT allow PC to update whilst Sub-PC loop running
+ # reset to zero
+ self.svstate.srcstep[0:7] = 0
+ print (" svstate.srcstep loop end (PC to update)")
+ self.pc.update_nia(self.is_svp64_mode)
+ self.namespace['NIA'] = self.pc.NIA
+
# UPDATE program counter
- self.pc.update(self.namespace)
+ self.pc.update(self.namespace, self.is_svp64_mode)
+ print("end of call", self.namespace['CIA'], self.namespace['NIA'])
def inject():
projects / soc.git / blobdiff