SVP64 Remap Fields structures for ISACaller

[soc.git] / src / soc / decoder / isa / caller.py

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 9252bfef12369e1851d01abd47886de68a177f5e..bd516ebb6d0d985bdb136ec12134f0908d7599aa 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -1,3 +1,7 @@
+# SPDX-License-Identifier: LGPLv3+
+# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020 Michael Nolan
+# Funded by NLnet http://nlnet.nl
 """core of the python-based POWER9 simulator
 
 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
@@ -16,7 +20,7 @@ from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
                                      insns, MicrOp)
-from soc.decoder.helpers import exts, gtu, ltu
+from soc.decoder.helpers import exts, gtu, ltu, undefined
 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
 
 from collections import namedtuple
@@ -208,6 +212,45 @@ class PC:
         namespace['NIA'] = self.NIA
 
 
+# Simple-V: see https://libre-soc.org/openpower/sv
+# also soc.sv.svstate SVSTATEREC
+class SVP64State:
+    def __init__(self, init=0):
+        self.spr = SelectableInt(init, 32)
+        # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
+        self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7))
+        self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
+        self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
+        self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
+        self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
+        self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
+
+
+# SVP64 ReMap field
+class SVP64RMFields:
+    def __init__(self, init=0):
+        self.spr = SelectableInt(init, 24)
+        # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
+        self.mmode = FieldSelectableInt(self.spr, [0])
+        self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
+        self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
+        self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
+        self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
+        self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
+        self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
+
+
+# SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
+class SPP64PrefixFields:
+    def __init__(self):
+        self.insn = SelectableInt(0, 32)
+        # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
+        self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
+        self.pid = FieldSelectableInt(self.insn, (7, 9) # must be 0b11
+        rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
+        self.rm = FieldSelectableInt(self.spr, rmfields)
+
+
 class SPR(dict):
     def __init__(self, dec2, initial_sprs={}):
         self.sd = dec2
@@ -274,6 +317,7 @@ class ISACaller:
     # respect_pc - tracks the program counter.  requires initial_insns
     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
                  initial_mem=None, initial_msr=0,
+                 initial_svstate=0,
                  initial_insns=None, respect_pc=False,
                  disassembly=None,
                  initial_pc=0,
@@ -314,6 +358,7 @@ class ISACaller:
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
+        self.svstate = SVSTATE(initial_svstate)
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 
@@ -336,7 +381,7 @@ class ISACaller:
         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 
         # "undefined", just set to variable-bit-width int (use exts "max")
-        self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
+        #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 
         self.namespace = {}
         self.namespace.update(self.spr)
@@ -348,7 +393,7 @@ class ISACaller:
                                'CIA': self.pc.CIA,
                                'CR': self.cr,
                                'MSR': self.msr,
-                               'undefined': self.undefined,
+                               'undefined': undefined,
                                'mode_is_64bit': True,
                                'SO': XER_bits['SO']
                                })